wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump fesvr for better loadmem impl. Fix verilator loadmem support

Browse Source
This commit is contained in:
Colin Schmidt
2020-08-05 09:55:31 -07:00
parent 93c7fef942
commit 5bfc289677
2 changed files with 3 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
generators/utilities/src/main/resources/csrc/emulator.cc
View File

@@ -116,7 +116,6 @@ int main(int argc, char** argv)
FILE * vcdfile = NULL; FILE * vcdfile = NULL;
uint64_t start = 0; uint64_t start = 0;
#endif #endif
char ** htif_argv = NULL;
int verilog_plusargs_legal = 1; int verilog_plusargs_legal = 1;
opterr = 1; opterr = 1;
@@ -252,10 +251,6 @@ done_processing:
usage(argv[0]); usage(argv[0]);
return 1; return 1;
} }
int htif_argc = 1 + argc - optind;
htif_argv = (char **) malloc((htif_argc) * sizeof (char *));
htif_argv[0] = argv[0];
for (int i = 1; optind < argc;) htif_argv[i++] = argv[optind++];
if (verbose) if (verbose)
fprintf(stderr, "using random seed %u\n", random_seed); fprintf(stderr, "using random seed %u\n", random_seed);
@@ -278,8 +273,8 @@ done_processing:
#endif #endif
jtag = new remote_bitbang_t(rbb_port); jtag = new remote_bitbang_t(rbb_port);
dtm = new dtm_t(htif_argc, htif_argv); dtm = new dtm_t(argc, argv);
tsi = new tsi_t(htif_argc, htif_argv); tsi = new tsi_t(argc, argv);
signal(SIGTERM, handle_sigterm); signal(SIGTERM, handle_sigterm);
@@ -364,6 +359,5 @@ done_processing:
if (tsi) delete tsi; if (tsi) delete tsi;
if (jtag) delete jtag; if (jtag) delete jtag;
if (tile) delete tile; if (tile) delete tile;
if (htif_argv) free(htif_argv);
return ret; return ret;
} }

2
toolchains/esp-tools/riscv-isa-sim

Submodule toolchains/esp-tools/riscv-isa-sim updated: 13384cac1e...2bc65d1bf6