[firesim] Initial Golden Gate support

generators/firechip/src/main/scala/SimConfigs.scala

@@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
   new FRFCFS16GBQuadRankLLC4MB3Div ++
   new FireSimConfig)
 
+class Midas2Config extends Config(
+  new WithMultiCycleRamModels ++
+  new FireSimConfig)
+

generators/firechip/src/main/scala/TargetMixins.scala

@@ -1,6 +1,7 @@
 package firesim.firesim
 
 import chisel3._
+import chisel3.experimental.annotate
 import freechips.rocketchip.config.{Field, Parameters}
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.tilelink._
@@ -12,7 +13,7 @@ import freechips.rocketchip.rocket.TracedInstruction
 import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
 
 import midas.models.AXI4BundleWithEdge
-import midas.targetutils.ExcludeInstanceAsserts
+import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
 
 /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
   *  associated with each port. This drives FASED functional model sizing
@@ -103,3 +104,27 @@ trait HasTraceIOImp extends LazyModuleImp {
 trait ExcludeInvalidBoomAssertions extends LazyModuleImp {
   ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb"))
 }
+
+trait CanHaveBoomMultiCycleRegfileImp {
+  val outer: boom.system.BoomRocketSubsystem
+  val cores = outer.boomTiles.map(tile => tile.module.core)
+  cores.foreach({ core =>
+    core.iregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+
+     if (core.fp_pipeline != null) core.fp_pipeline.fregfile match {
+      case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile))
+      case _ => Nil
+    }
+
+   })
+}
+trait CanHaveRocketMultiCycleRegfileImp {
+  val outer: RocketSubsystem
+  outer.rocketTiles.foreach({ tile =>
+    annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf))
+    tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
+  })
+}

generators/firechip/src/main/scala/Targets.scala

@@ -55,6 +55,7 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l)
     with HasPeripheryIceNICModuleImpValidOnly
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveRocketMultiCycleRegfileImp
 
 
 class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem
@@ -79,6 +80,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod
     with HasPeripheryUARTModuleImp
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
+    with CanHaveRocketMultiCycleRegfileImp
 
 
 class FireBoom(implicit p: Parameters) extends Subsystem
@@ -106,6 +108,7 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveBoomMultiCycleRegfileImp
 
 class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
     with HasHierarchicalBusTopology
@@ -130,6 +133,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI
     with HasPeripheryBlockDeviceModuleImp
     with HasTraceIOImp
     with ExcludeInvalidBoomAssertions
+    with CanHaveBoomMultiCycleRegfileImp
 
 case object NumNodes extends Field[Int]
 

generators/firechip/src/test/scala/ScalaTestSuite.scala

@@ -109,9 +109,9 @@ abstract class FireSimTestSuite(
         val lines = Source.fromFile(file).getLines.toList
         lines.filter(_.startsWith("TRACEPORT")).drop(dropLines)
       }
-      val resetLength = 50
+      val resetLength = 51
       val verilatedOutput  = getLines(new File(outDir,  s"/${verilatedLog}"))
-      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1)
+      val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
       assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
       assert(verilatedOutput.nonEmpty)
       for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
@@ -131,8 +131,9 @@ abstract class FireSimTestSuite(
 }
 
 class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
-class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig")
 class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
 class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
   runSuite("verilator")(NICLoopbackTests)
 }
+class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
+class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")