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Merge pull request #979 from ucb-bar/ibex-integration

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Ibex integration
This commit is contained in:
Abraham Gonzalez
2021-11-23 23:04:58 -08:00
committed by GitHub
parent fc994c4822 cf1df5fd7b
commit 5b3b388843
17 changed files with 97 additions and 16 deletions
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6
.circleci/check-commit.sh
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@@ -48,13 +48,13 @@ search () {
done
}
submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
dir="generators"
if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
then
branches=("master")
branches=("master" "main")
else
branches=("master" "dev")
branches=("master" "main" "dev")
fi
search

12
.circleci/config.yml
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@@ -252,6 +252,13 @@ jobs:
group-key: "group-cores"
project-key: "chipyard-sodor"
timeout: "30m"
chipyard-ibex-run-tests:
executor: main-env
steps:
- run-tests:
group-key: "group-cores"
project-key: "chipyard-ibex"
timeout: "30m"
chipyard-multiclock-rocket-run-tests:
executor: main-env
steps:
@@ -309,7 +316,7 @@ jobs:
tools-version: "esp-tools"
group-key: "group-accels"
project-key: "chipyard-hwacha"
timeout: "30m"
timeout: "60m"
chipyard-gemmini-run-tests:
executor: main-env
steps:
@@ -455,6 +462,9 @@ workflows:
- chipyard-sodor-run-tests:
requires:
- prepare-chipyard-cores
- chipyard-ibex-run-tests:
requires:
- prepare-chipyard-cores
- chipyard-dmirocket-run-tests:
requires:
- prepare-chipyard-peripherals

3
.circleci/defaults.sh
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@@ -49,7 +49,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -71,6 +71,7 @@ mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"

3
.circleci/run-tests.sh
View File

@@ -100,6 +100,9 @@ case $1 in
chipyard-sodor)
run_asm ${mapping[$1]}
;;
chipyard-ibex)
run_bmark ${mapping[$1]} #TODO: Find 32-bit test
;;
chipyard-nvdla)
make -C $LOCAL_CHIPYARD_DIR/tests
make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary

6
.github/scripts/check-commit.sh vendored
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@@ -47,13 +47,13 @@ search () {
done
}
submodules=("cva6" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
submodules=("cva6" "ibex" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
dir="generators"
if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
then
branches=("master")
branches=("master" "main")
else
branches=("master" "dev")
branches=("master" "main" "dev")
fi
search

3
.github/scripts/defaults.sh vendored
View File

@@ -37,7 +37,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
# key value store to get the build groups
declare -A grouping
grouping["group-cores"]="chipyard-cva6 chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
grouping["group-cores"]="chipyard-cva6 chipyard-ibex chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor chipyard-digitaltop chipyard-multiclock-rocket"
grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -59,6 +59,7 @@ mapping["chipyard-blkdev"]=" CONFIG=SimBlockDeviceRocketConfig"
mapping["chipyard-hwacha"]=" CONFIG=HwachaRocketConfig"
mapping["chipyard-gemmini"]=" CONFIG=GemminiRocketConfig"
mapping["chipyard-cva6"]=" CONFIG=CVA6Config"
mapping["chipyard-ibex"]=" CONFIG=IbexConfig"
mapping["chipyard-spiflashread"]=" CONFIG=LargeSPIFlashROMRocketConfig"
mapping["chipyard-spiflashwrite"]=" CONFIG=SmallSPIFlashRocketConfig"
mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"

3
.github/scripts/run-tests.sh vendored
View File

@@ -101,6 +101,9 @@ case $1 in
chipyard-cva6)
make run-binary-fast -C $LOCAL_SIM_DIR $DISABLE_SIM_PREREQ ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
;;
chipyard-ibex)
run_bmark ${mapping[$1]} #TODO: Find 32-bit test
;;
chipyard-sodor)
run_asm ${mapping[$1]}
;;

22
.github/workflows/chipyard-run-tests.yml vendored
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@@ -329,6 +329,26 @@ jobs:
project-key: "chipyard-cva6"
- uses: ./.github/actions/job-end
chipyard-ibex-run-tests:
name: chipyard-ibex-run-tests
needs: prepare-chipyard-cores
runs-on: ubuntu-latest
container:
image: ucbbar/chipyard-ci-image:554b436
options: --entrypoint /bin/bash
steps:
- name: Checkout
uses: actions/checkout@v2
- uses: ./.github/actions/job-start
id: job-start
- name: Run tests
if: steps.job-start.outputs.run_result != 'success'
uses: ./.github/actions/run-tests
with:
group-key: "group-cores"
project-key: "chipyard-ibex"
- uses: ./.github/actions/job-end
chipyard-sodor-run-tests:
name: chipyard-sodor-run-tests
needs: prepare-chipyard-cores
@@ -690,7 +710,7 @@ jobs:
all_tests_passed:
name: "all tests passed"
needs: [commit-on-master-check, tutorial-setup-check, documentation-check,
chipyard-rocket-run-tests, chipyard-hetero-run-tests, chipyard-boom-run-tests, chipyard-cva6-run-tests,
chipyard-rocket-run-tests, chipyard-hetero-run-tests, chipyard-boom-run-tests, chipyard-cva6-run-tests, chipyard-ibex-run-tests,
chipyard-sodor-run-tests, chipyard-dmirocket-run-tests, chipyard-spiflashwrite-run-tests,
chipyard-spiflashread-run-tests, chipyard-lbwif-run-tests, chipyard-sha3-run-tests,
chipyard-streaming-fir-run-tests, chipyard-streaming-passthrough-run-tests, chipyard-hwacha-run-tests,

3
.gitmodules vendored
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@@ -140,3 +140,6 @@
[submodule "tools/rocket-dsp-utils"]
path = tools/rocket-dsp-utils
url = https://github.com/ucb-bar/rocket-dsp-utils
[submodule "generators/ibex"]
path = generators/ibex
url = https://github.com/ucb-bar/ibex-wrapper

7
build.sbt
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@@ -186,7 +186,7 @@ lazy val chipyard = (project in file("generators/chipyard"))
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -218,6 +218,11 @@ lazy val cva6 = (project in file("generators/cva6"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val ibex = (project in file("generators/ibex"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val sodor = (project in file("generators/riscv-sodor"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)

4
docs/Chipyard-Basics/Chipyard-Components.rst
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@@ -24,6 +24,10 @@ Processor Cores
An in-order RISC-V core written in System Verilog. Previously called Ariane.
See :ref:`Generators/CVA6:CVA6 Core` for more information.
**Ibex Core**
An in-order 32 bit RISC-V core written in System Verilog.
See :ref:`Generators/Ibex:Ibex Core` for more information.
Accelerators
^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^

14
docs/Generators/Ibex.rst Normal file
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@@ -0,0 +1,14 @@
Ibex Core
====================================
`Ibex <https://github.com/lowRISC/ibex>`__ is a parameterizable RV32IMC embedded core written in SystemVerilog, currently maintained by `lowRISC <https://lowrisc.org>`__.
The `Ibex core` is wrapped in an `Ibex tile` so it can be used with the `Rocket Chip SoC generator`.
The core exposes a custom memory interface, interrupt ports, and other misc. ports that are connected from within the tile to TileLink buses and other parameterization signals.
.. Warning:: The Ibex mtvec register is 256 byte aligned. When writing/running tests, ensure that the trap vector is also 256 byte aligned.
.. Warning:: The Ibex reset vector is located at BOOT_ADDR + 0x80.
While the core itself is not a generator, we expose the same parameterization that the Ibex core provides so that all supported Ibex configurations are available.
For more information, see the `GitHub repository for Ibex <https://github.com/lowRISC/ibex>`__.

1
docs/Generators/index.rst
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@@ -28,6 +28,7 @@ so changes to the generators themselves will automatically be used when building
SiFive-Generators
SHA3
CVA6
Ibex
NVDLA
Sodor

15
generators/chipyard/src/main/scala/config/IbexConfigs.scala Normal file
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@@ -0,0 +1,15 @@
package chipyard
import chisel3._
import freechips.rocketchip.config.{Config}
// ---------------------
// Ibex Configs
// ---------------------
// Multi-core and 32b heterogeneous configs are supported
class IbexConfig extends Config(
new ibex.WithNIbexCores(1) ++
new chipyard.config.AbstractConfig)

1
generators/ibex Submodule

Submodule generators/ibex added at bdf41a0548

2
generators/testchipip

Submodule generators/testchipip updated: 0743c5a941...5917176c91

8
scripts/tutorial-patches/build.sbt.patch
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@@ -1,5 +1,5 @@
diff --git a/build.sbt b/build.sbt
index 3123c4b8..487fc428 100644
index b1f7e004..f39c3712 100644
--- a/build.sbt
+++ b/build.sbt
@@ -184,7 +184,7 @@ lazy val testchipipLib = "edu.berkeley.cs" %% "testchipip" % "1.0-020719-SNAPSHO
@@ -7,11 +7,11 @@ index 3123c4b8..487fc428 100644
.sourceDependency(testchipip, testchipipLib)
.dependsOn(rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+// sha3, // On separate line to allow for cleaner tutorial-setup patches
+ //sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor)
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex)
.settings(libraryDependencies ++= rocketLibDeps.value)
@@ -223,11 +223,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
@@ -228,11 +228,11 @@ lazy val sodor = (project in file("generators/riscv-sodor"))
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)