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Merge pull request #6 from ucb-bar/local-fpga-support-docs

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Local fpga support docs
This commit is contained in:
Abraham Gonzalez
2020-11-06 21:03:15 -08:00
committed by GitHub
parent a9b9054120 8fb76dda7b
commit 5a4cad0172
6 changed files with 172 additions and 7 deletions
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3
fpga/src/main/scala/arty/Configs.scala
View File

@@ -26,7 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => {
debugIdleCycles = 5)
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractArty and Rocket
class WithArtyTweaks extends Config(
new WithArtyJTAGHarnessBinder ++
new WithArtyUARTHarnessBinder ++
@@ -41,3 +41,4 @@ class WithArtyTweaks extends Config(
class TinyRocketArtyConfig extends Config(
new WithArtyTweaks ++
new chipyard.TinyRocketConfig)
// DOC include start: AbstractArty and Rocket

2
fpga/src/main/scala/vcu118/Configs.scala
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@@ -51,6 +51,7 @@ class WithSystemModifications extends Config((site, here, up) => {
case SerialTLKey => None // remove serialized tl port
})
// DOC include start: AbstractVCU118 and Rocket
class WithVCU118Tweaks extends Config(
new WithUART ++
new WithSPISDCard ++
@@ -66,6 +67,7 @@ class WithVCU118Tweaks extends Config(
class RocketVCU118Config extends Config(
new WithVCU118Tweaks ++
new chipyard.RocketConfig)
// DOC include end: AbstractVCU118 and Rocket
class BoomVCU118Config extends Config(
new WithFPGAFrequency(75) ++

4
fpga/src/main/scala/vcu118/TestHarness.scala
View File

@@ -41,6 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val topDesign = LazyModule(p(BuildTop)(dp))
// DOC include start: ClockOverlay
// place all clocks in the shell
require(dp(ClockInputOverlayKey).size >= 1)
val sysClkNode = dp(ClockInputOverlayKey)(0).place(ClockInputDesignInput()).overlayOutput.node
@@ -56,13 +57,16 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
val dutWrangler = LazyModule(new ResetWrangler)
val dutGroup = ClockGroup()
dutClock := dutWrangler.node := dutGroup := harnessSysPLL
// DOC include end: ClockOverlay
/*** UART ***/
// DOC include start: UartOverlay
// 1st UART goes to the VCU118 dedicated UART
val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head)))
dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb))
// DOC include end: UartOverlay
/*** SPI ***/