From 255e88fe8f8a0ee5e2b648403d0d6b872d75e1d1 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 17:06:34 -0800 Subject: [PATCH 1/6] Initial outline of FPGA prototyping docs --- docs/Chipyard-Basics/Chipyard-Components.rst | 11 ++- docs/Simulation/FPGA-Prototyping.rst | 87 ++++++++++++++++++++ docs/Simulation/index.rst | 11 ++- fpga/src/main/scala/vcu118/Configs.scala | 2 + fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 5 files changed, 107 insertions(+), 6 deletions(-) create mode 100644 docs/Simulation/FPGA-Prototyping.rst diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst index c24f81ed..1d19a65f 100644 --- a/docs/Chipyard-Basics/Chipyard-Components.rst +++ b/docs/Chipyard-Basics/Chipyard-Components.rst @@ -106,12 +106,12 @@ Software Sims ------------------------------------------- -**verilator (Verilator wrapper)** +**Verilator** Verilator is an open source Verilog simulator. The ``verilator`` directory provides wrappers which construct Verilator-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd waveform files). See :ref:`Verilator (Open-Source)` for more information. -**vcs (VCS wrapper)** +**VCS** VCS is a proprietary Verilog simulator. Assuming the user has valid VCS licenses and installations, the ``vcs`` directory provides wrappers which construct VCS-based simulators from relevant generated RTL, allowing for execution of test RISC-V programs on the simulator (including vcd/vpd waveform files). See :ref:`Synopsys VCS (License Required)` for more information. @@ -124,6 +124,13 @@ Sims In order to use FireSim, the repository must be cloned and executed on AWS instances. See :ref:`FireSim` for more information. +**FPGA Prototyping** + FPGA prototyping is supported in Chipyard using SiFive's ``fpga-shells``. + Some examples of FPGA's supported are Arty and VCU118. + For more accurate and deterministic simulation results, please consider using the :ref:`FireSim` platform. + See :ref:`FPGA Prototyping` for more information. + + VLSI ------------------------------------------- diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst new file mode 100644 index 00000000..eab33d35 --- /dev/null +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -0,0 +1,87 @@ +FPGA Prototyping +============================== + +FPGA Prototyping +----------------------- + +Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . +This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. + +Setup +----- + +All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +To initialize the ``fpga-shells`` repository, run the included submodule script: + +.. code-block:: shell + + # in the chipyard top level folder + ./scripts/init-fpga.sh + +Making a Bitstream +------------------ + +Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. +Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. + +.. code-block:: shell + + make SBT_PROJECT=... MODEL=... VLOG_MODEL=... MODEL_PACKAGE=... CONFIG=... CONFIG_PACKAGE=... GENERATOR_PACKAGE=... TB=... TOP=... bit + + # or + + make SUB_PROJECT= bit + +By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. +These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. +For example, building the BOOM configuration on the VCU118: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + +Running a Design on Arty +------------------------ + +Running a Design on VCU118 +-------------------------- + +Basic Design +~~~~~~~~~~~~ + +The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. +To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. +Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala + :language: scala + :start-after: DOC include start: AbstractVCU118 and Rocket + :end-before: DOC include end: AbstractVCU118 and Rocket + +fpga-shells / Overlays / HarnessBinders +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. +The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. +``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. +First ``Overlays`` must be "placed" which adds them to the design. +For example, the following shows a UART overlay being placed into the design. + +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: UartOverlay + :end-before: DOC include end: UartOverlay + +Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. +The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. +This is similar to all the other ``Overlays``. +They must be "placed" and given a set of inputs (IOs, parameters). + +Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. +This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. +For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. + +An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index c15283d3..24099bfb 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -1,16 +1,18 @@ Simulation ======================= -Chipyard supports two classes of simulation: +Chipyard supports three classes of simulation: -#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators +#. Software RTL simulation using commercial or open-source (Verilator) RTL simulators #. FPGA-accelerated full-system simulation using FireSim +#. FPGA prototyping on ``fpga-shells`` platforms Software RTL simulators of Chipyard designs run at O(1 KHz), but compile -quickly and provide full waveforms. Conversly, FPGA-accelerated simulators run +quickly and provide full waveforms. Conversely, FPGA-accelerated simulators and FPGA prototyping run at O(100 MHz), making them appropriate for booting an operating system and running a complete workload, but have multi-hour compile times and poorer debug -visability. +visibility. However, FPGA-accelerated simulators differ from FPGA prototyping by providing deterministic +cycle-accurate results. Click next to see how to run a simulation. @@ -20,4 +22,5 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulation + FPGA-Prototyping diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala index f55c9520..6822b251 100644 --- a/fpga/src/main/scala/vcu118/Configs.scala +++ b/fpga/src/main/scala/vcu118/Configs.scala @@ -48,6 +48,7 @@ class WithSystemModifications extends Config((site, here, up) => { case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(size = site(VCU118DDRSize)))) }) +// DOC include start: AbstractVCU118 and Rocket class AbstractVCU118Config extends Config( new WithUART ++ new WithSPISDCard ++ @@ -72,6 +73,7 @@ class AbstractVCU118Config extends Config( class RocketVCU118Config extends Config( new freechips.rocketchip.subsystem.WithNBigCores(1) ++ new AbstractVCU118Config) +// DOC include end: AbstractVCU118 and Rocket class BoomVCU118Config extends Config( new WithFPGAFrequency(75) ++ diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index d5a5481e..05e1e59d 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -70,10 +70,12 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S /*** UART ***/ +// DOC include start: UartOverlay // 1st UART goes to the VCU118 dedicated UART val io_uart_bb = BundleBridgeSource(() => (new UARTPortIO(dp(PeripheryUARTKey).head))) dp(UARTOverlayKey).head.place(UARTDesignInput(io_uart_bb)) +// DOC include end: UartOverlay /*** SPI ***/ From 84508bee6e075db9181ed4ad2b3bc76a43852e91 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 5 Nov 2020 21:51:25 -0800 Subject: [PATCH 2/6] More FPGA prototyping docs --- docs/Simulation/FPGA-Prototyping.rst | 74 +++++++++++++------- fpga/src/main/scala/vcu118/TestHarness.scala | 2 + 2 files changed, 51 insertions(+), 25 deletions(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eab33d35..0594b132 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -2,16 +2,21 @@ FPGA Prototyping ============================== FPGA Prototyping ------------------------ +---------------- -Chipyard supports FPGA prototyping for local FPGAs supported under ``fpga-shells`` . -This include popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. +Chipyard supports FPGA prototyping for local FPGAs supported by `fpga-shells `__. +This includes popular FPGAs such as the Xilinx VCU118 and the Xilinx Arty board. FPGA prototyping allows RTL-level simulation at orders-of-magnitude faster speeds than software RTL simulators at the cost of slower compile times. -Setup ------ +.. Note:: While ``fpga-shells`` also supports Xilinx VC707 and some MicroSemi PolarFire boards, currently only the VCU118 and Arty boards are explicitly supported in Chipyard. + However, using the VCU118/Arty examples would be useful to see how to implement VC707/PolarFire support. -All FPGA related collateral is located in the ``fpga`` top-level Chipyard folder. +Sources and Submodule Setup +--------------------------- + +All FPGA related collateral and sources are located in the ``fpga`` top-level Chipyard folder. +This includes ``fpga-shells`` and the ``src`` folders that hold both Scala, TCL and other collateral. +However, the ``fpga-shells`` repository is not initialized by default. To initialize the ``fpga-shells`` repository, run the included submodule script: .. code-block:: shell @@ -22,8 +27,8 @@ To initialize the ``fpga-shells`` repository, run the included submodule script: Making a Bitstream ------------------ -Making a bitstream for any FPGA is similar to building RTL for a software RTL simulation. -Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software RTL Simulation` section you can run the following command in the ``fpga`` directory. +Making a bitstream for any FPGA target is similar to building RTL for a software RTL simulation. +Similar to a software RTL simulation (:ref:`Simulating A Custom Project`), you can run the following command in the ``fpga`` directory to build a bitstream: .. code-block:: shell @@ -35,12 +40,16 @@ Similar to the :ref:`Simulating A Custom Project` section in the :ref:`Software By default a couple of ``SUB_PROJECT``'s are already defined for use, including ``vcu118`` and ``arty``. These default ``SUB_PROJECT``'s setup the necessary test harnesses, packages, and more. +Like a software RTL simulation make invocation, all of the make variables can be overridden with user specific values (i.e. include the ``SUB_PROJECT`` with a ``CONFIG`` and ``CONFIG_PACKAGE`` override). In most cases, you will just need to run a command with a ``SUB_PROJECT`` and an overridden ``CONFIG`` to point to. For example, building the BOOM configuration on the VCU118: .. code-block:: shell - make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config bit + +That command will build the RTL and generate a bitstream using Vivado. +However, like a software RTL simulation, you can also run the intermediate make steps to just generate Verilog or FIRRTL. Running a Design on Arty ------------------------ @@ -51,24 +60,24 @@ Running a Design on VCU118 Basic Design ~~~~~~~~~~~~ -The default VCU118 design is setup to run RISC-V Linux from an SDCard while piping the terminal over UART. -To change the design, you can create your own configuration and add the ``AbstractVCU118Config`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. -Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory. -Notice that the majority of config. fragments in ``AbstractVCU118Config`` are shared with a normal Chipyard config. +The default VCU118 FPGA target design is setup to have UART, a SPI SDCard, and DDR backing memory. +This allows it to run RISC-V Linux from an SDCard while piping the terminal over UART to the host machine (the machine connected to the VCU118). +To extend this design, you can create your own Chipyard configuration and add the ``WithVCU118Tweaks`` located in ``fpga/src/main/scala/vcu118/Configs.scala``. +Adding this config. fragment will enable and connect the UART, SPI SDCard, and DDR backing memory to your Chipyard design/config. .. literalinclude:: ../../fpga/src/main/scala/vcu118/Configs.scala :language: scala :start-after: DOC include start: AbstractVCU118 and Rocket :end-before: DOC include end: AbstractVCU118 and Rocket -fpga-shells / Overlays / HarnessBinders -~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ +Brief Implementation Description + More Complicated Designs +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -To make meaningful VCU118 changes (adding new IOs, connecting to different VCU118 ports, etc), the ``VCU118TestHarness`` must change. -The ``VCU118TestHarness`` uses ``fpga-shells`` to add ``Overlays`` that connect to the VCU118 external IOs. -``fpga/src/main/scala/vcu118/TestHarness.scala`` shows an example of using these ``Overlays``. -First ``Overlays`` must be "placed" which adds them to the design. -For example, the following shows a UART overlay being placed into the design. +The basis for a VCU118 design revolves around creating a special test harness to connect the external IOs to your Chipyard design. +This is done with the ``VCU118TestHarness`` in the basic default VCU118 FPGA target. +The ``VCU118TestHarness`` (located in ``fpga/src/main/scala/vcu118/TestHarness.scala``) uses ``Overlays`` that connect to the VCU118 external IOs. +Generally, the ``Overlays`` take an IO from the ``ChipTop`` (labeled as ``topDesign`` in the file) when "placed" and connect it to the external IO and generate necessary Vivado collateral. +For example, the following shows a UART ``Overlay`` being "placed" into the design with a IO input called ``io_uart_bb``. .. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala :language: scala @@ -76,12 +85,27 @@ For example, the following shows a UART overlay being placed into the design. :end-before: DOC include end: UartOverlay Here the ``UARTOverlayKey`` is referenced and used to "place" the necessary connections (and collateral) to connect to the UART. -The ``UARTDesignInput`` is used to pass in the UART signals used to connect to the external UART IO. -This is similar to all the other ``Overlays``. +The ``UARTDesignInput`` is used to pass in the UART IO from the ``ChipTop``/``topDesign`` to the ``Overlay``. +Note that the ``BundleBridgeSource`` can be viewed as a glorified wire (that is defined in the ``LazyModule`` scope). +This pattern is similar for all other ``Overlays`` in the test harness. They must be "placed" and given a set of inputs (IOs, parameters). +The main exception to this pattern is the ``Overlay`` used to generate the clock(s) for the FPGA. -Once you add the wanted ``Overlays`` and place them into a new ``TestHarness``, you can add a new set of harness/io binders to connect to them. -This is shown in ``fpga/src/main/scala/vcu118/HarnessBinders.scala``. -For more information on harness and IO binders, refer to :ref:`IOBinders and HarnessBinders`. +.. literalinclude:: ../../fpga/src/main/scala/vcu118/TestHarness.scala + :language: scala + :start-after: DOC include start: ClockOverlay + :end-before: DOC include end: ClockOverlay + +Without going into too much detail, the clocks overlay is placed in the harness and a PLL node (``harnessSysPLL``) generates the necessary clocks specified by ``ClockSinkNodes``. +For ease of use, you can change the ``FPGAFrequencyKey`` to change the default clock frequency of the FPGA design. + +After the harness is created, the ``BundleBridgeSource``'s must be connected to the ``ChipTop`` IOs. +This is done with harness binders and io binders (see ``fpga/src/main/scala/vcu118/HarnessBinders.scala`` and ``fpga/src/main/scala/vcu118/IOBinders.scala``). +For more information on harness binders and io binders, refer to :ref:`IOBinders and HarnessBinders`. An example of a more complicated design using new ``Overlays`` can be viewed in ``fpga/src/main/scala/vcu118/bringup/``. +This example extends the default test harness and creates new ``Overlays`` to connect to the FMC port. + +.. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. + For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. + See :ref:`Making a Bitstream` for information on the various make variables. diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala index 05e1e59d..ed4ba221 100644 --- a/fpga/src/main/scala/vcu118/TestHarness.scala +++ b/fpga/src/main/scala/vcu118/TestHarness.scala @@ -41,6 +41,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val topDesign = LazyModule(p(BuildTop)(dp)) +// DOC include start: ClockOverlay // place all clocks in the shell dp(ClockInputOverlayKey).foreach { _.place(ClockInputDesignInput()) } @@ -59,6 +60,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S val dutWrangler = LazyModule(new ResetWrangler) val dutGroup = ClockGroup() dutClock := dutWrangler.node := dutGroup := harnessSysPLL +// DOC include end: ClockOverlay // connect ref clock to dummy sink node ref_clock.get() match { From b7ef84860583bca6948f14d1518235077454de71 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Fri, 6 Nov 2020 11:13:27 -0800 Subject: [PATCH 3/6] Add some docs on debugging --- docs/Simulation/FPGA-Prototyping.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index 0594b132..ba53a0b7 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -109,3 +109,19 @@ This example extends the default test harness and creates new ``Overlays`` to co .. Note:: Remember that since whenever a new test harness is created (or the config. changes, or the config. packages changes, or...), you need to modify the make invocation. For example, ``make SUB_PROJECT=vcu118 CONFIG=MyNewVCU118Config CONFIG_PACKAGE=this.is.my.scala.package bit``. See :ref:`Making a Bitstream` for information on the various make variables. + +Debugging with ILAs +~~~~~~~~~~~~~~~~~~~ + +Adding an ILA can be added to the design for debugging relevant signals. +First, open up the post synthesis checkpoint located in the build directory for your design in Vivado (it should be labeled ``post_synth.dcp``). +Then using Vivado, add ILAs (and other debugging tools) for your design (search online for more information on how to add an ILA). +After the changes are made, save the checkpoint and run the make invocation with the ``debug-bitstream`` target: +be done by modifying the post synthesis checkpoint, saving it, and running ``make ... debug-bitstream``. +For example, running the bitstream build for an added ILA for a BOOM config.: + +.. code-block:: shell + + make SUB_PROJECT=vcu118 CONFIG=BoomVCU118Config debug-bitstream + +For more extensive debugging tools for FPGA simulations including printf synthesis, assert synthesis, instruction traces, ILAs, out-of-band profiling, co-simulation, and more, please refer to the :ref:`FireSim` platform. From 98fcea7b572e2c0456a9f74096cea3b2482997c9 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 17:25:05 -0800 Subject: [PATCH 4/6] Adding initial Arty documentation; will be expanded further. --- docs/Simulation/FPGA-Prototyping.rst | 15 +++++++++++++++ fpga/src/main/scala/arty/Configs.scala | 3 ++- 2 files changed, 17 insertions(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ba53a0b7..ed07a7f4 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -54,6 +54,21 @@ However, like a software RTL simulation, you can also run the intermediate make Running a Design on Arty ------------------------ +Basic Design +~~~~~~~~~~~~ + +The default Arty FPGA target design is setup to have JTAG, UART, SPI, and I2C available over the board's GPIO pins. The pin mappings of these interfaces are identical to those described in the `SiFive Freedom E310 Arty Getting Started Guide `__. +The JTAG interface allows a user to connect to the core over OpenOCD, run bare-metal applications, and debug using gdb. +To extend this design, you can create your own Chipyard configuration and add the ``WithArtyTweaks`` located in ``fpga/src/main/scala/arty/Configs.scala``. +Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2C interfaces to your Chipyard design/config. + +.. literalinclude:: ../../fpga/src/main/scala/arty/Configs.scala + :language: scala + :start-after: DOC include start: AbstractArty and Rocket + :end-before: DOC include end: AbstractArty and Rocket + +Future peripherals to be supported include the Arty's SPI Flash EEPROM. + Running a Design on VCU118 -------------------------- diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala index bc62bcf9..61a6234c 100644 --- a/fpga/src/main/scala/arty/Configs.scala +++ b/fpga/src/main/scala/arty/Configs.scala @@ -26,7 +26,7 @@ class WithDefaultPeripherals extends Config((site, here, up) => { debugIdleCycles = 5) case SerialTLKey => None // remove serialized tl port }) - +// DOC include start: AbstractArty and Rocket class WithArtyTweaks extends Config( new WithArtyJTAGHarnessBinder ++ new WithArtyUARTHarnessBinder ++ @@ -41,3 +41,4 @@ class WithArtyTweaks extends Config( class TinyRocketArtyConfig extends Config( new WithArtyTweaks ++ new chipyard.TinyRocketConfig) +// DOC include start: AbstractArty and Rocket From e20311da84d85178ad0a2b16fd0a642feb2bc4a5 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 19:58:52 -0800 Subject: [PATCH 5/6] Adding implementation details for the Arty. --- docs/Simulation/FPGA-Prototyping.rst | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index ed07a7f4..eacf3982 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -69,6 +69,12 @@ Adding this config. fragment will enable and connect the JTAG, UART, SPI, and I2 Future peripherals to be supported include the Arty's SPI Flash EEPROM. +Brief Implementation Description for Less Complicated Designs (Such as Arty), and Guidance for Adding/Changing Xilinx Collateral +~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + +Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. + Running a Design on VCU118 -------------------------- From 8fb76dda7babad128f76d121bfd77c5155fbfa24 Mon Sep 17 00:00:00 2001 From: James Dunn Date: Fri, 6 Nov 2020 20:00:29 -0800 Subject: [PATCH 6/6] Fixed syntax. --- docs/Simulation/FPGA-Prototyping.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/Simulation/FPGA-Prototyping.rst b/docs/Simulation/FPGA-Prototyping.rst index eacf3982..6f82446e 100644 --- a/docs/Simulation/FPGA-Prototyping.rst +++ b/docs/Simulation/FPGA-Prototyping.rst @@ -73,7 +73,7 @@ Brief Implementation Description for Less Complicated Designs (Such as Arty), an ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ Like the VCU118, the basis for the Arty design is the creation of a special test harness that connects the external IO (which exist as Xilinx IP blackboxes) to the Chipyard design. -This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlay``s, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlay``s, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinder``s and ssIOBinder``s. +This is done with the ``ArtyTestHarness`` in the basic default Arty target. However, unlike the ``VCU118TestHarness``, the ``ArtyTestHarness`` uses no ``Overlays``, and instead directly connects chip top IO to the ports of the external IO blackboxes, using functions such as ``IOBUF`` provided by ``fpga-shells``. Unlike the VCU118 and other more complicated test harnesses, the Arty's Vivado collateral is not generated by ``Overlays``, but rather are a static collection of ``create_ip`` and ``set_properties`` statements located in the files within ``fpga/fpga-shells/xilinx/arty/tcl`` and ``fpga/fpga-shells/xilinx/arty/constraints``. If the user wishes to re-map FPGA package pins to different harness-level IO, this may be changed within ``fpga/fpga-shells/xilinx/arty/constraints/arty-master.xdc``. The addition of new Xilinx IP blocks may be done in ``fpga-shells/xilinx/arty/tcl/ip.tcl``, mapped to harness-level IOs in ``arty-master.xdc``, and wired through from the test harness to the chip top using ``HarnessBinders`` and ``IOBinders``. Running a Design on VCU118 --------------------------