rename OUT_DIR to GEN_COLLATERAL_DIR

2023-02-13 13:24:04 -08:00
parent 6cd46d3c73
commit 58a6e72528
7 changed files with 29 additions and 29 deletions
--- a/common.mk
+++ b/common.mk
@@ -91,7 +91,7 @@ endif
 #########################################################################################
 # copy over bootrom files
 #########################################################################################
-$(build_dir) $(OUT_DIR):
+$(build_dir) $(GEN_COLLATERAL_DIR):
 	mkdir -p $@

 $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip/bootrom/bootrom.%.img | $(build_dir)
@@ -172,7 +172,7 @@ endif
 		--no-dedup \
 		--output-file $(SFC_FIRRTL_BASENAME) \
 		--output-annotation-file $(SFC_ANNO_FILE) \
-		--target-dir $(OUT_DIR) \
+		--target-dir $(GEN_COLLATERAL_DIR) \
 		--input-file $(FIRRTL_FILE) \
 		--annotation-file $(FINAL_ANNO_FILE) \
 		--log-level $(FIRRTL_LOGLEVEL) \
@@ -198,7 +198,7 @@ endif
 		--repl-seq-mem-circuit=$(MODEL) \
 		--annotation-file=$(SFC_ANNO_FILE) \
 		--split-verilog \
-		-o $(OUT_DIR) \
+		-o $(GEN_COLLATERAL_DIR) \
 		$(SFC_FIRRTL_FILE)
 	-mv $(SFC_SMEMS_CONF) $(MFC_SMEMS_CONF)
 	$(SED) -i 's/.*/& /' $(MFC_SMEMS_CONF) # need trailing space for SFC macrocompiler
@@ -211,8 +211,8 @@ $(TOP_MODS_FILELIST) $(MODEL_MODS_FILELIST) $(ALL_MODS_FILELIST) $(BB_MODS_FILEL
 		--out-dut-filelist $(TOP_MODS_FILELIST) \
 		--out-model-filelist $(MODEL_MODS_FILELIST) \
 		--in-all-filelist $(MFC_FILELIST) \
-		--target-dir $(OUT_DIR)
-	$(SED) -e 's;^;$(OUT_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST)
+		--target-dir $(GEN_COLLATERAL_DIR)
+	$(SED) -e 's;^;$(GEN_COLLATERAL_DIR)/;' $(MFC_BB_MODS_FILELIST) > $(BB_MODS_FILELIST)
 	$(SED) -i 's/\.\///' $(TOP_MODS_FILELIST)
 	$(SED) -i 's/\.\///' $(MODEL_MODS_FILELIST)
 	$(SED) -i 's/\.\///' $(BB_MODS_FILELIST)
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -94,14 +94,14 @@ SIM_FILE_REQS += \
 	$(ROCKETCHIP_RSRCS_DIR)/vsrc/EICG_wrapper.v

 # copy files but ignore *.h files in *.f (match vcs)
-$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR)
-	rm -rf $(OUT_DIR)/*
-	cp -f $(SIM_FILE_REQS) $(OUT_DIR)
+$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	rm -rf $(GEN_COLLATERAL_DIR)/*
+	cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
 	$(foreach file,\
 		$(SIM_FILE_REQS),\
 		$(if $(filter %.h,$(file)),\
 			,\
-			echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
+			echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))

 #########################################################################################
 # import other necessary rules and variables
--- a/sims/common-sim-flags.mk
+++ b/sims/common-sim-flags.mk
@@ -20,7 +20,7 @@ SIM_CXXFLAGS = \
 	-std=c++17 \
 	-I$(RISCV)/include \
 	-I$(dramsim_dir) \
-	-I$(OUT_DIR) \
+	-I$(GEN_COLLATERAL_DIR) \
 	$(EXTRA_SIM_CXXFLAGS)

 SIM_LDFLAGS = \
--- a/sims/vcs/Makefile
+++ b/sims/vcs/Makefile
@@ -38,14 +38,14 @@ SIM_FILE_REQS += \
 	$(ROCKETCHIP_RSRCS_DIR)/vsrc/TestDriver.v

 # copy files but ignore *.h files in *.f since vcs has +incdir+$(build_dir)
-$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR)
-	rm -rf $(OUT_DIR)/*
-	cp -f $(SIM_FILE_REQS) $(OUT_DIR)
+$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	rm -rf $(GEN_COLLATERAL_DIR)/*
+	cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
 	$(foreach file,\
 		$(SIM_FILE_REQS),\
 		$(if $(filter %.h,$(file)),\
 			,\
-			echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
+			echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))

 #########################################################################################
 # import other necessary rules and variables
--- a/sims/verilator/Makefile
+++ b/sims/verilator/Makefile
@@ -66,14 +66,14 @@ SIM_FILE_REQS += \
 	$(ROCKETCHIP_RSRCS_DIR)/csrc/remote_bitbang.cc

 # copy files and add -FI for *.h files in *.f
-$(sim_files): $(SIM_FILE_REQS) $(OUT_DIR)
-	rm -rf $(OUT_DIR)/*
-	cp -f $(SIM_FILE_REQS) $(OUT_DIR)
+$(sim_files): $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
+	rm -rf $(GEN_COLLATERAL_DIR)/*
+	cp -f $(SIM_FILE_REQS) $(GEN_COLLATERAL_DIR)
 	$(foreach file,\
 		$(SIM_FILE_REQS),\
 		$(if $(filter %.h,$(file)),\
-			echo "-FI $(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;,\
-			echo "$(addprefix $(OUT_DIR)/, $(notdir $(file)))" >> $@;))
+			echo "-FI $(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;,\
+			echo "$(addprefix $(GEN_COLLATERAL_DIR)/, $(notdir $(file)))" >> $@;))

 #########################################################################################
 # import other necessary rules and variables
@@ -144,7 +144,7 @@ CHIPYARD_VERILATOR_FLAGS := \
 # options dependent on whether external IP (cva6/NVDLA) or just chipyard is used
 # NOTE: defer the evaluation of this until it is used!
 PLATFORM_OPTS = $(shell \
-	if grep -qiP "module\s+(CVA6|NVDLA)" $(OUT_DIR)/*.*v; \
+	if grep -qiP "module\s+(CVA6|NVDLA)" $(GEN_COLLATERAL_DIR)/*.*v; \
 	then echo "$(VERILOG_IP_VERILATOR_FLAGS)"; \
 	else echo "$(CHIPYARD_VERILATOR_FLAGS)"; fi)

@@ -182,7 +182,7 @@ VERILATOR_CXXFLAGS = \
 	-DTEST_HARNESS=V$(VLOG_MODEL) \
 	-DVERILATOR \
 	-include $(build_dir)/$(long_name).plusArgs \
-	-include $(OUT_DIR)/verilator.h
+	-include $(GEN_COLLATERAL_DIR)/verilator.h

 VERILATOR_LDFLAGS = $(SIM_LDFLAGS)

--- a/variables.mk
+++ b/variables.mk
@@ -161,18 +161,18 @@ MFC_TOP_HRCHY_JSON ?= $(build_dir)/top_module_hierarchy.json
 MFC_MODEL_HRCHY_JSON ?= $(build_dir)/model_module_hierarchy.json
 MFC_SMEMS_CONF ?= $(build_dir)/$(long_name).mems.conf
 # hardcoded firtool outputs
-MFC_FILELIST = $(OUT_DIR)/filelist.f
-MFC_BB_MODS_FILELIST = $(OUT_DIR)/firrtl_black_box_resource_files.f
-MFC_TOP_SMEMS_JSON = $(OUT_DIR)/metadata/seq_mems.json
-MFC_MODEL_SMEMS_JSON = $(OUT_DIR)/metadata/tb_seq_mems.json
+MFC_FILELIST = $(GEN_COLLATERAL_DIR)/filelist.f
+MFC_BB_MODS_FILELIST = $(GEN_COLLATERAL_DIR)/firrtl_black_box_resource_files.f
+MFC_TOP_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/seq_mems.json
+MFC_MODEL_SMEMS_JSON = $(GEN_COLLATERAL_DIR)/metadata/tb_seq_mems.json

 # macrocompiler smems in/output
 SFC_SMEMS_CONF ?= $(build_dir)/$(long_name).sfc.mems.conf
 TOP_SMEMS_CONF ?= $(build_dir)/$(long_name).top.mems.conf
-TOP_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).top.mems.v
+TOP_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).top.mems.v
 TOP_SMEMS_FIR  ?= $(build_dir)/$(long_name).top.mems.fir
 MODEL_SMEMS_CONF ?= $(build_dir)/$(long_name).model.mems.conf
-MODEL_SMEMS_FILE ?= $(OUT_DIR)/$(long_name).model.mems.v
+MODEL_SMEMS_FILE ?= $(GEN_COLLATERAL_DIR)/$(long_name).model.mems.v
 MODEL_SMEMS_FIR  ?= $(build_dir)/$(long_name).model.mems.fir

 # top module files to include
@@ -254,7 +254,7 @@ gen_dir=$(sim_dir)/generated-src
 # per-project output directory
 build_dir=$(gen_dir)/$(long_name)
 # final generated collateral per-project
-OUT_DIR ?= $(build_dir)/gen-collateral
+GEN_COLLATERAL_DIR ?= $(build_dir)/gen-collateral

 #########################################################################################
 # assembly/benchmark variables
--- a/vcs.mk
+++ b/vcs.mk
@@ -51,7 +51,7 @@ VCS_NONCC_OPTS = \
 	-sverilog +systemverilogext+.sv+.svi+.svh+.svt -assert svaext +libext+.sv \
 	+v2k +verilog2001ext+.v95+.vt+.vp +libext+.v \
 	-debug_pp \
-	+incdir+$(OUT_DIR)
+	+incdir+$(GEN_COLLATERAL_DIR)

 PREPROC_DEFINES = \
 	+define+VCS \