wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge pull request #259 from ucb-bar/alon-docs-dev

Browse Source 
fix docs bugs
This commit is contained in:
Abraham Gonzalez
2019-09-25 20:37:36 -07:00
committed by GitHub
parent 7edf0a9c1c c224b3f921
commit 58105c78dd
2 changed files with 8 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
docs/Quick-Start.rst
View File

@@ -48,7 +48,7 @@ This depends on what you are planning to do with Chipyard.
* If you intend to run a simulation of one of the vanilla Chipyard examples, go to :ref:`sw-rtl-sim-intro` and follow the instructions.
* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`sw-sim-custom` and follow the instructions.
* If you intend to run a simulation of a custom Chipyard SoC Configuration, go to :ref:`Simulating A Custom Project` and follow the instructions.
* If you intend to run a full-system FireSim simulation, go to :ref:`firesim-sim-intro` and follow the instructions.
@@ -56,8 +56,8 @@ This depends on what you are planning to do with Chipyard.
* If you want to learn about the structure of Chipyard, go to :ref:`chipyard-components`.
* If you intend to build one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.
* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`.
* If you intend to run a VLSI flow using one of the vanilla Chipyard examples, go to <> and follow the instructions.
* If you intend to change the generators (BOOM, Rocket, etc) themselves, see :ref:`generator-index`.
* If you intend to build a chip using one of the vanilla Chipyard examples, go to :ref:`build-a-chip` and follow the instructions.

9
docs/Simulation/Software-RTL-Simulation.rst
View File

@@ -27,6 +27,7 @@ Choice of Simulator
First, we will start by entering the Verilator or VCS directory:
For an open-source Verilator simulation, enter the ``sims/verilator`` directory
.. code-block:: shell
# Enter Verilator directory
@@ -41,6 +42,7 @@ For a proprietry VCS simulation, enter the ``sims/vcs`` directory
.. _sim-default:
Simulating The Default Example
-------------------------------
@@ -71,8 +73,9 @@ For example:
.. _sw-sim-custom:
Simulating A Custom Project
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
-------------------------------
If you later create your own project, you can use environment variables to build an alternate configuration.
@@ -86,9 +89,7 @@ Each of these make variables correspond to a particular part of the design/codeb
The ``SBT_PROJECT`` is the ``build.sbt`` project that holds all of the source files and that will be run during the RTL build.
The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design.
Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
The ``MODEL`` and ``VLOG_MODEL`` are the top-level class names of the design. Normally, these are the same, but in some cases these can differ (if the Chisel class differs than what is emitted in the Verilog).
The ``MODEL_PACKAGE`` is the Scala package (in the Scala code that says ``package ...``) that holds the ``MODEL`` class.