wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Bump to July 2020 rocketchip

Browse Source
This commit is contained in:
Jerry Zhao
2020-08-03 14:23:08 -07:00
parent fdfef878af
commit 578ae6fca2
19 changed files with 142 additions and 119 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
generators/tracegen/src/main/scala/System.scala
View File

@@ -12,6 +12,10 @@ class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil
val tileStatusNodes = tiles.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
override lazy val module = new TraceGenSystemModuleImp(this)
}
@@ -20,12 +24,8 @@ class TraceGenSystemModuleImp(outer: TraceGenSystem)
{
val success = IO(Output(Bool()))
outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U }
val status = dontTouch(DebugCombiner(outer.tileStatusNodes.map(_.bundle)))
val status = dontTouch(DebugCombiner(outer.tiles.collect {
case t: GroundTestTile => t.module.status
case t: BoomTraceGenTile => t.module.status
}))
success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
}

10
generators/tracegen/src/main/scala/Tile.scala
View File

@@ -3,7 +3,7 @@ package tracegen
import chisel3._
import chisel3.util._
import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType, BundleBridgeSource}
import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
@@ -206,11 +206,13 @@ class BoomTraceGenTile private(
val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val statusNode = BundleBridgeSource(() => new GroundTestStatus)
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params))
val dcache = LazyModule(new BoomNonBlockingDCache(staticIdForMetadataUseOnly)(boom_params))
val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
@@ -220,11 +222,11 @@ class BoomTraceGenTile private(
class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){
val status = IO(new GroundTestStatus)
val status = outer.statusNode.bundle
val halt_and_catch_fire = None
val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := constants.hartid
tracegen.io.hartid := outer.hartIdSinkNode.bundle
val ptw = Module(new DummyPTW(1))
val lsu = Module(new LSU()(outer.boom_params, outer.dcache.module.edge))