Merge branch 'dev' into heterofix
This commit is contained in:
Jerry Zhao
@@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then
|
||||
cd $HOME
|
||||
|
||||
# init all submodules including the tools
|
||||
CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1
|
||||
CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=2 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1
|
||||
fi
|
||||
|
||||
@@ -7,7 +7,7 @@ version: 2
|
||||
jobs:
|
||||
commit-on-master-check:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -19,7 +19,7 @@ jobs:
|
||||
.circleci/check-commit.sh
|
||||
install-riscv-toolchain:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -31,19 +31,19 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- run:
|
||||
name: Building riscv-tools toolchain
|
||||
command: |
|
||||
.circleci/build-toolchains.sh riscv-tools
|
||||
no_output_timeout: 120m
|
||||
- save_cache:
|
||||
key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
key: riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
paths:
|
||||
- "/home/riscvuser/riscv-tools-install"
|
||||
install-esp-toolchain:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -55,19 +55,19 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
|
||||
- esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }}
|
||||
- run:
|
||||
name: Building esp-tools toolchain
|
||||
command: |
|
||||
.circleci/build-toolchains.sh esp-tools
|
||||
no_output_timeout: 120m
|
||||
- save_cache:
|
||||
key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
|
||||
key: esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }}
|
||||
paths:
|
||||
- "/home/riscvuser/esp-tools-install"
|
||||
install-verilator:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -90,7 +90,7 @@ jobs:
|
||||
- "/home/riscvuser/verilator"
|
||||
build-extra-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -105,7 +105,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- run:
|
||||
name: Build extra tests
|
||||
command: .circleci/build-extra-tests.sh
|
||||
@@ -116,7 +116,7 @@ jobs:
|
||||
- "/home/riscvuser/project/tests"
|
||||
prepare-example:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -131,7 +131,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -145,7 +145,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-boomrocketexample:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -160,7 +160,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -174,7 +174,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-boom:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -189,7 +189,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -203,7 +203,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-rocketchip:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -218,7 +218,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -232,7 +232,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-blockdevrocketchip:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -247,7 +247,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -261,7 +261,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-hwacha:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -276,7 +276,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
|
||||
- esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -290,7 +290,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-firesim:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -305,7 +305,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -319,7 +319,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-fireboom:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -334,7 +334,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -348,7 +348,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
prepare-firesim-clockdiv:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -363,7 +363,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -377,7 +377,7 @@ jobs:
|
||||
- "/home/riscvuser/project"
|
||||
midasexamples-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -389,7 +389,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }}
|
||||
@@ -398,7 +398,7 @@ jobs:
|
||||
command: .circleci/run-midasexamples-tests.sh
|
||||
example-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -410,7 +410,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- example-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -422,7 +422,7 @@ jobs:
|
||||
command: .circleci/run-tests.sh example
|
||||
boomrocketexample-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -434,7 +434,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- boomrocketexample-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -446,7 +446,7 @@ jobs:
|
||||
command: .circleci/run-tests.sh boomrocketexample
|
||||
boom-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -458,7 +458,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- boom-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -470,7 +470,7 @@ jobs:
|
||||
command: .circleci/run-tests.sh boom
|
||||
rocketchip-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -482,7 +482,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- rocketchip-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -494,7 +494,7 @@ jobs:
|
||||
command: .circleci/run-tests.sh rocketchip
|
||||
hwacha-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -506,7 +506,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }}
|
||||
- esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- hwacha-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -518,7 +518,7 @@ jobs:
|
||||
command: .circleci/run-tests.sh hwacha
|
||||
firesim-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -530,7 +530,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- firesim-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -545,7 +545,7 @@ jobs:
|
||||
command: .circleci/run-firesim-tests.sh firesim
|
||||
fireboom-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -557,7 +557,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- fireboom-{{ .Branch }}-{{ .Revision }}
|
||||
@@ -573,7 +573,7 @@ jobs:
|
||||
no_output_timeout: 20m
|
||||
firesim-clockdiv-run-tests:
|
||||
docker:
|
||||
- image: riscvboom/riscvboom-images:0.0.10
|
||||
- image: riscvboom/riscvboom-images:0.0.11
|
||||
environment:
|
||||
JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit
|
||||
TERM: dumb
|
||||
@@ -585,7 +585,7 @@ jobs:
|
||||
.circleci/create-hash.sh
|
||||
- restore_cache:
|
||||
keys:
|
||||
- riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }}
|
||||
- riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }}
|
||||
- restore_cache:
|
||||
keys:
|
||||
- firesim-clockdiv-{{ .Branch }}-{{ .Revision }}
|
||||
|
||||
@@ -4,6 +4,7 @@
|
||||
|
||||
# turn echo on and error on earliest command
|
||||
set -ex
|
||||
set -o pipefail
|
||||
|
||||
# get shared variables
|
||||
SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )"
|
||||
@@ -12,10 +13,10 @@ source $SCRIPT_DIR/defaults.sh
|
||||
# enter bhd repo
|
||||
cd $LOCAL_CHIPYARD_DIR
|
||||
|
||||
# get the version of riscv-tools from the git submodule hash
|
||||
git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash
|
||||
git submodule status | grep "esp-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/esp-tools.hash
|
||||
|
||||
# Use normalized output of git-submodule status as hashfile
|
||||
for tools in 'riscv-tools' 'esp-tools' ; do
|
||||
git submodule status "toolchains/${tools}" "toolchains/qemu" | while read -r line ; do
|
||||
echo "${line#[!0-9a-f]}"
|
||||
done > "${HOME}/${tools}.hash"
|
||||
done
|
||||
echo "Hashfile for riscv-tools and esp-tools created in $HOME"
|
||||
echo "Contents: riscv-tools:$(cat $HOME/riscv-tools.hash)"
|
||||
echo "Contents: esp-tools:$(cat $HOME/esp-tools.hash)"
|
||||
|
||||
@@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig"
|
||||
mapping["rocketchip"]="SUB_PROJECT=rocketchip"
|
||||
mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice"
|
||||
mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha"
|
||||
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig"
|
||||
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig"
|
||||
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig"
|
||||
mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
|
||||
mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config"
|
||||
mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config"
|
||||
|
||||
1
.gitignore
vendored
1
.gitignore
vendored
@@ -12,5 +12,6 @@ target
|
||||
.DS_Store
|
||||
env.sh
|
||||
riscv-tools-install
|
||||
esp-tools-install
|
||||
tags
|
||||
*~
|
||||
|
||||
50
.gitmodules
vendored
50
.gitmodules
vendored
@@ -34,12 +34,37 @@
|
||||
[submodule "generators/block-inclusivecache-sifive"]
|
||||
path = generators/sifive-cache
|
||||
url = https://github.com/sifive/block-inclusivecache-sifive.git
|
||||
[submodule "toolchains/riscv-tools"]
|
||||
path = toolchains/riscv-tools
|
||||
url = https://github.com/freechipsproject/rocket-tools.git
|
||||
[submodule "toolchains/esp-tools"]
|
||||
path = toolchains/esp-tools
|
||||
url = https://github.com/ucb-bar/esp-tools.git
|
||||
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"]
|
||||
path = toolchains/riscv-tools/riscv-gnu-toolchain
|
||||
url = https://github.com/riscv/riscv-gnu-toolchain.git
|
||||
[submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"]
|
||||
path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt
|
||||
url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git
|
||||
shallow = true
|
||||
[submodule "toolchains/riscv-tools/riscv-isa-sim"]
|
||||
path = toolchains/riscv-tools/riscv-isa-sim
|
||||
url = https://github.com/riscv/riscv-isa-sim.git
|
||||
[submodule "toolchains/riscv-tools/riscv-pk"]
|
||||
path = toolchains/riscv-tools/riscv-pk
|
||||
url = https://github.com/riscv/riscv-pk.git
|
||||
[submodule "toolchains/riscv-tools/riscv-tests"]
|
||||
path = toolchains/riscv-tools/riscv-tests
|
||||
url = https://github.com/riscv/riscv-tests.git
|
||||
[submodule "toolchains/riscv-tools/riscv-openocd"]
|
||||
path = toolchains/riscv-tools/riscv-openocd
|
||||
url = https://github.com/riscv/riscv-openocd.git
|
||||
[submodule "toolchains/esp-tools/riscv-gnu-toolchain"]
|
||||
path = toolchains/esp-tools/riscv-gnu-toolchain
|
||||
url = https://github.com/ucb-bar/esp-gnu-toolchain.git
|
||||
[submodule "toolchains/esp-tools/riscv-isa-sim"]
|
||||
path = toolchains/esp-tools/riscv-isa-sim
|
||||
url = https://github.com/ucb-bar/esp-isa-sim.git
|
||||
[submodule "toolchains/esp-tools/riscv-pk"]
|
||||
path = toolchains/esp-tools/riscv-pk
|
||||
url = https://github.com/riscv/riscv-pk.git
|
||||
[submodule "toolchains/esp-tools/riscv-tests"]
|
||||
path = toolchains/esp-tools/riscv-tests
|
||||
url = https://github.com/ucb-bar/esp-tests.git
|
||||
[submodule "vlsi/hammer"]
|
||||
path = vlsi/hammer
|
||||
url = https://github.com/ucb-bar/hammer.git
|
||||
@@ -52,18 +77,21 @@
|
||||
[submodule "tools/treadle"]
|
||||
path = tools/treadle
|
||||
url = https://github.com/freechipsproject/treadle.git
|
||||
[submodule "generators/rocc-template"]
|
||||
[submodule "generators/sha3"]
|
||||
path = generators/sha3
|
||||
url = https://github.com/ucb-bar/rocc-template.git
|
||||
url = https://github.com/ucb-bar/sha3.git
|
||||
[submodule "tools/firrtl-interpreter"]
|
||||
path = tools/firrtl-interpreter
|
||||
url = https://github.com/freechipsproject/firrtl-interpreter.git
|
||||
[submodule "vlsi/hammer-cadence-plugins"]
|
||||
path = vlsi/hammer-cadence-plugins
|
||||
url = git@github.com:ucb-bar/hammer-cadence-plugins.git
|
||||
url = https://github.com/ucb-bar/hammer-cadence-plugins.git
|
||||
[submodule "vlsi/hammer-synopsys-plugins"]
|
||||
path = vlsi/hammer-synopsys-plugins
|
||||
url = git@github.com:ucb-bar/hammer-synopsys-plugins.git
|
||||
url = https://github.com/ucb-bar/hammer-synopsys-plugins.git
|
||||
[submodule "vlsi/hammer-mentor-plugins"]
|
||||
path = vlsi/hammer-mentor-plugins
|
||||
url = git@github.com:ucb-bar/hammer-mentor-plugins.git
|
||||
url = https://github.com/ucb-bar/hammer-mentor-plugins.git
|
||||
[submodule "toolchains/qemu"]
|
||||
path = toolchains/qemu
|
||||
url = https://github.com/qemu/qemu.git
|
||||
|
||||
@@ -23,6 +23,7 @@ lazy val commonSettings = Seq(
|
||||
addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full),
|
||||
unmanagedBase := (chipyardRoot / unmanagedBase).value,
|
||||
allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"),
|
||||
exportJars := true,
|
||||
resolvers ++= Seq(
|
||||
Resolver.sonatypeRepo("snapshots"),
|
||||
Resolver.sonatypeRepo("releases"),
|
||||
@@ -188,7 +189,7 @@ lazy val midas = ProjectRef(firesimDir, "midas")
|
||||
lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
|
||||
|
||||
lazy val firechip = (project in file("generators/firechip"))
|
||||
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
|
||||
.dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
|
||||
.settings(
|
||||
commonSettings,
|
||||
testGrouping in Test := isolateAllTests( (definedTests in Test).value )
|
||||
|
||||
89
docs/Advanced-Concepts/Debugging-RTL.rst
Normal file
89
docs/Advanced-Concepts/Debugging-RTL.rst
Normal file
@@ -0,0 +1,89 @@
|
||||
Debugging RTL
|
||||
======================
|
||||
|
||||
While the packaged Chipyard configs and RTL have been tested to work,
|
||||
users will typically want to build custom chips by adding their own
|
||||
IP, or by modifying existing Chisel generators. Such changes might introduce
|
||||
bugs. This section aims to run through a typical debugging flow
|
||||
using Chipyard. We assume the user has a custom SoC configuration,
|
||||
and is trying to verify functionality by running some software test.
|
||||
We also assume the software has already been verified on a functional
|
||||
simulator, such as Spike or QEMU. This section will focus on debugging
|
||||
hardware.
|
||||
|
||||
Waveforms
|
||||
---------------------------
|
||||
|
||||
The default software RTL simulators do not dump waveforms during execution.
|
||||
To build simulators with wave dump capabilities use must use the ``debug``
|
||||
make target. For example:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=CustomConfig debug
|
||||
|
||||
The ``run-binary-debug`` rule will also automatically build a simulator,
|
||||
run it on a custom binary, and generate a waveform. For example, to run a
|
||||
test on ``helloworld.riscv``, use
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv
|
||||
|
||||
VCS and Verilator also support many additional flags. For example, specifying
|
||||
the ``+vpdfilesize`` flag in VCS will treat the output file as a circular
|
||||
buffer, saving disk space for long-running simulations. Refer to the VCS
|
||||
and Verilator manuals for more information You may use the ``SIM_FLAGS``
|
||||
make variable to set additional simulator flags:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=CustomConfig run-binary-debug BINARY=linux.riscv SIM_FLAGS=+vpdfilesize=1024
|
||||
|
||||
Print Output
|
||||
---------------------------
|
||||
|
||||
Both Rocket and BOOM can be configured with varying levels of print output.
|
||||
For information see the Rocket core source code, or the BOOM `documentation
|
||||
<https://docs.boom-core.org/en/latest/>`__ .website. In addition, developers
|
||||
may insert arbitrary printfs at arbitrary conditions within the Chisel g
|
||||
enerators. See the Chisel documentation for information on this.
|
||||
|
||||
Once the cores have been configured with the desired print statements, the
|
||||
``+verbose`` flag will cause the simulator to print the statements. The following
|
||||
commands will all generate desired print statements:
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv
|
||||
# The below command does the same thing
|
||||
./simv-CustomConfig-debug +verbose helloworld.riscv
|
||||
|
||||
Both cores can be configured to print out commit logs, which can then be compared
|
||||
against a Spike commit log to verify correctness.
|
||||
|
||||
Basic tests
|
||||
---------------------------
|
||||
``riscv-tests`` includes basic ISA-level tests and basic benchmarks. These
|
||||
are used in Chipyard CI, and should be the first step in verifying a chip's
|
||||
functionality. The make rule is
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
make CONFIG=CustomConfig run-asm-tests run-bmark-tests
|
||||
|
||||
|
||||
Torture tests
|
||||
---------------------------
|
||||
The RISC-V torture utility generates random RISC-V assembly streams, compiles them,
|
||||
runs them on both the Spike functional model and the SW simulator, and verifies
|
||||
identical program behavior. The torture utility can also be configured to run
|
||||
continuously for stress-testing. The torture utility exists within the ``utilities``
|
||||
directory.
|
||||
|
||||
Firesim Debugging
|
||||
---------------------------
|
||||
Chisel printfs, asserts, and waveform generation are also available in FireSim
|
||||
FPGA-accelerated simulation. See the FireSim
|
||||
`documentation <https://docs.fires.im/en/latest/>`__ for more detail.
|
||||
|
||||
@@ -10,4 +10,5 @@ They expect you to know about Chisel, Parameters, Configs, etc.
|
||||
|
||||
Top-Testharness
|
||||
Chip-Communication
|
||||
Debugging-RTL
|
||||
Resources
|
||||
|
||||
@@ -18,3 +18,5 @@ Hit next to get started!
|
||||
Chipyard-Components
|
||||
Configs-Parameters-Mixins
|
||||
Initial-Repo-Setup
|
||||
|
||||
|
||||
|
||||
@@ -5,8 +5,10 @@ Requirements
|
||||
-------------------------------------------
|
||||
|
||||
Chipyard is developed and tested on Linux-based systems.
|
||||
It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
|
||||
Working under Windows is not recommended.
|
||||
|
||||
.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``.
|
||||
|
||||
.. Warning:: Working under Windows is not recommended.
|
||||
|
||||
Setting up the Chipyard Repo
|
||||
-------------------------------------------
|
||||
|
||||
@@ -87,4 +87,4 @@ will look as follows:
|
||||
You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG``
|
||||
variables. Note that if your target machine has I/O not provided in the default
|
||||
FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need
|
||||
to write a custom endpoint.
|
||||
to write a custom bridge.
|
||||
|
||||
@@ -20,3 +20,4 @@ Click next to see how to run a simulation.
|
||||
|
||||
Software-RTL-Simulation
|
||||
FPGA-Accelerated-Simulators
|
||||
|
||||
|
||||
@@ -1,5 +1,6 @@
|
||||
FireMarshal
|
||||
=================
|
||||
``software/firemarshal``
|
||||
|
||||
FireMarshal is a workload generation tool for RISC-V based systems. It
|
||||
currently only supports the FireSim FPGA-accelerated simulation platform.
|
||||
|
||||
@@ -54,8 +54,9 @@ Prerequisites
|
||||
* Genus, Innovus, and Calibre licenses
|
||||
* For ASAP7 specifically:
|
||||
|
||||
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it
|
||||
* Download the `ASAP7 PDK <http://asap.asu.edu/asap/>`__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you.
|
||||
* If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion.
|
||||
* Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded).
|
||||
|
||||
Initial Setup
|
||||
-------------
|
||||
@@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u
|
||||
|
||||
make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB
|
||||
|
||||
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead.
|
||||
The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches).
|
||||
|
||||
The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module.
|
||||
|
||||
@@ -98,7 +99,7 @@ example-vlsi
|
||||
^^^^^^^^^^^^
|
||||
This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow.
|
||||
|
||||
The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4.
|
||||
The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4.
|
||||
|
||||
example.yml
|
||||
^^^^^^^^^^^
|
||||
@@ -126,6 +127,14 @@ Intermediate database are written in ``build/par-rundir`` between each step of t
|
||||
|
||||
Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files.
|
||||
|
||||
`gdspy` can be used to `view the final layout <https://gdspy.readthedocs.io/en/stable/reference.html?highlight=scale#layoutviewer>`__, but it is somewhat crude and slow (wait a few minutes for it to load):
|
||||
|
||||
.. code-block:: shell
|
||||
|
||||
``python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds``
|
||||
|
||||
By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names.
|
||||
|
||||
DRC & LVS
|
||||
^^^^^^^^^
|
||||
To run DRC & LVS, and view the results in Calibre:
|
||||
|
||||
76
generators/firechip/src/main/scala/BridgeBinders.scala
Normal file
76
generators/firechip/src/main/scala/BridgeBinders.scala
Normal file
@@ -0,0 +1,76 @@
|
||||
//See LICENSE for license details.
|
||||
|
||||
package firesim.firesim
|
||||
|
||||
import chisel3._
|
||||
|
||||
import freechips.rocketchip.config.{Field, Config}
|
||||
import freechips.rocketchip.diplomacy.{LazyModule}
|
||||
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
|
||||
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp}
|
||||
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
|
||||
|
||||
import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp}
|
||||
import icenet.HasPeripheryIceNICModuleImpValidOnly
|
||||
|
||||
import junctions.{NastiKey, NastiParameters}
|
||||
import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
|
||||
import firesim.bridges._
|
||||
import firesim.configs.MemModelKey
|
||||
import firesim.util.RegisterBridgeBinder
|
||||
|
||||
class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp =>
|
||||
target.debug.clockeddmi.foreach({ cdmi =>
|
||||
cdmi.dmi.req.valid := false.B
|
||||
cdmi.dmi.req.bits := DontCare
|
||||
cdmi.dmi.resp.ready := false.B
|
||||
cdmi.dmiClock := false.B.asClock
|
||||
cdmi.dmiReset := false.B
|
||||
})
|
||||
Seq()
|
||||
})
|
||||
|
||||
class WithSerialBridge extends RegisterBridgeBinder({
|
||||
case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p))
|
||||
})
|
||||
|
||||
class WithNICBridge extends RegisterBridgeBinder({
|
||||
case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p))
|
||||
})
|
||||
|
||||
class WithUARTBridge extends RegisterBridgeBinder({
|
||||
case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p))
|
||||
})
|
||||
|
||||
class WithBlockDeviceBridge extends RegisterBridgeBinder({
|
||||
case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p))
|
||||
})
|
||||
|
||||
class WithFASEDBridge extends RegisterBridgeBinder({
|
||||
case t: CanHaveMasterAXI4MemPortModuleImp =>
|
||||
implicit val p = t.p
|
||||
(t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) =>
|
||||
(io zip node.in).map({ case (axi4Bundle, (_, edge)) =>
|
||||
val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth,
|
||||
axi4Bundle.ar.bits.addr.getWidth,
|
||||
axi4Bundle.ar.bits.id.getWidth)
|
||||
FASEDBridge(axi4Bundle, t.reset.toBool,
|
||||
CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge))))
|
||||
})
|
||||
}).toSeq
|
||||
})
|
||||
|
||||
class WithTracerVBridge extends RegisterBridgeBinder({
|
||||
case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p)
|
||||
})
|
||||
|
||||
// Shorthand to register all of the provided bridges above
|
||||
class WithDefaultFireSimBridges extends Config(
|
||||
new WithTiedOffDebug ++
|
||||
new WithSerialBridge ++
|
||||
new WithNICBridge ++
|
||||
new WithUARTBridge ++
|
||||
new WithBlockDeviceBridge ++
|
||||
new WithFASEDBridge ++
|
||||
new WithTracerVBridge
|
||||
)
|
||||
@@ -2,7 +2,7 @@
|
||||
|
||||
package firesim.firesim
|
||||
|
||||
import java.io.{File}
|
||||
import java.io.{File, FileWriter}
|
||||
|
||||
import chisel3.experimental.RawModule
|
||||
import chisel3.internal.firrtl.{Circuit, Port}
|
||||
@@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu
|
||||
}
|
||||
|
||||
object FireSimGenerator extends App with IsFireSimGeneratorLike {
|
||||
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
|
||||
lazy val generatorArgs = GeneratorArgs(args)
|
||||
lazy val genDir = new File(names.targetDir)
|
||||
elaborateAndCompileWithMidas
|
||||
// The only reason this is not generateFirrtl; generateAnno is that we need to use a different
|
||||
// JsonProtocol to properly write out the annotations. Fix once the generated are unified
|
||||
elaborate
|
||||
generateTestSuiteMakefrags
|
||||
generateHostVerilogHeader
|
||||
generateArtefacts
|
||||
generateTclEnvFile
|
||||
}
|
||||
|
||||
// For now, provide a separate generator app when not specifically building for FireSim
|
||||
|
||||
@@ -1,58 +0,0 @@
|
||||
//See LICENSE for license details.
|
||||
package firesim.firesim
|
||||
|
||||
import freechips.rocketchip.config.{Parameters, Config, Field}
|
||||
|
||||
import midas.{EndpointKey}
|
||||
import midas.widgets.{EndpointMap}
|
||||
import midas.models._
|
||||
|
||||
import firesim.endpoints._
|
||||
import firesim.configs._
|
||||
|
||||
/*******************************************************************************
|
||||
* Full PLATFORM_CONFIG Configurations. These set simulator parameters.
|
||||
*
|
||||
* In general, if you're adding or removing features from any of these, you
|
||||
* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager
|
||||
* will store this name as part of the tags for the AGFI, so that later you can
|
||||
* reconstruct what is in a particular AGFI. These tags are also used to
|
||||
* determine which driver to build.
|
||||
*******************************************************************************/
|
||||
class FireSimConfig extends Config(
|
||||
new WithSerialWidget ++
|
||||
new WithUARTWidget ++
|
||||
new WithSimpleNICWidget ++
|
||||
new WithBlockDevWidget ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithTracerVWidget ++
|
||||
new BasePlatformConfig)
|
||||
|
||||
class FireSimClockDivConfig extends Config(
|
||||
new WithDefaultMemModel(clockDivision = 2) ++
|
||||
new FireSimConfig)
|
||||
|
||||
class FireSimDDR3Config extends Config(
|
||||
new FCFS16GBQuadRank ++
|
||||
new FireSimConfig)
|
||||
|
||||
class FireSimDDR3LLC4MBConfig extends Config(
|
||||
new FCFS16GBQuadRankLLC4MB ++
|
||||
new FireSimConfig)
|
||||
|
||||
class FireSimDDR3FRFCFSConfig extends Config(
|
||||
new FRFCFS16GBQuadRank ++
|
||||
new FireSimConfig)
|
||||
|
||||
class FireSimDDR3FRFCFSLLC4MBConfig extends Config(
|
||||
new FRFCFS16GBQuadRankLLC4MB ++
|
||||
new FireSimConfig)
|
||||
|
||||
class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config(
|
||||
new FRFCFS16GBQuadRankLLC4MB3Div ++
|
||||
new FireSimConfig)
|
||||
|
||||
class Midas2Config extends Config(
|
||||
new WithMultiCycleRamModels ++
|
||||
new FireSimConfig)
|
||||
|
||||
@@ -12,12 +12,16 @@ import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.devices.tilelink.BootROMParams
|
||||
import freechips.rocketchip.devices.debug.DebugModuleParams
|
||||
import boom.common.BoomTilesKey
|
||||
import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig}
|
||||
import testchipip.{BlockDeviceKey, BlockDeviceConfig}
|
||||
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
|
||||
import scala.math.{min, max}
|
||||
import tracegen.TraceGenKey
|
||||
import icenet._
|
||||
|
||||
import firesim.bridges._
|
||||
import firesim.util.{WithNumNodes}
|
||||
import firesim.configs._
|
||||
|
||||
class WithBootROM extends Config((site, here, up) => {
|
||||
case BootROMParams => {
|
||||
val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img")
|
||||
@@ -37,12 +41,14 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
|
||||
})
|
||||
|
||||
class WithUARTKey extends Config((site, here, up) => {
|
||||
case PeripheryUARTKey => List(UARTParams(
|
||||
case PeripheryUARTKey => List(UARTParams(
|
||||
address = BigInt(0x54000000L),
|
||||
nTxEntries = 256,
|
||||
nRxEntries = 256))
|
||||
})
|
||||
|
||||
class WithBlockDevice extends Config(new testchipip.WithBlockDevice)
|
||||
|
||||
class WithNICKey extends Config((site, here, up) => {
|
||||
case NICKey => NICConfig(
|
||||
inBufFlits = 8192,
|
||||
@@ -80,6 +86,14 @@ class WithScalaTestFeatures extends Config((site, here, up) => {
|
||||
case PrintTracePort => true
|
||||
})
|
||||
|
||||
// FASED Config Aliases. This to enable config generation via "_" concatenation
|
||||
// which requires that all config classes be defined in the same package
|
||||
class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB
|
||||
class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div
|
||||
|
||||
// L2 Config Aliases. For use with "_" concatenation
|
||||
class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache
|
||||
|
||||
/*******************************************************************************
|
||||
* Full TARGET_CONFIG configurations. These set parameters of the target being
|
||||
* simulated.
|
||||
@@ -101,6 +115,8 @@ class FireSimRocketChipConfig extends Config(
|
||||
new WithRocketL2TLBs(1024) ++
|
||||
new WithPerfCounters ++
|
||||
new WithoutClockGating ++
|
||||
new WithDefaultMemModel ++
|
||||
new WithDefaultFireSimBridges ++
|
||||
new freechips.rocketchip.system.DefaultConfig)
|
||||
|
||||
class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => {
|
||||
@@ -130,6 +146,13 @@ class FireSimRocketChipOctaCoreConfig extends Config(
|
||||
new WithNDuplicatedRocketCores(8) ++
|
||||
new FireSimRocketChipSingleCoreConfig)
|
||||
|
||||
// SHA-3 accelerator config
|
||||
class FireSimRocketChipSha3L2Config extends Config(
|
||||
new WithInclusiveCache ++
|
||||
new sha3.WithSha3Accel ++
|
||||
new WithNBigCores(1) ++
|
||||
new FireSimRocketChipConfig)
|
||||
|
||||
class FireSimBoomConfig extends Config(
|
||||
new WithBootROM ++
|
||||
new WithPeripheryBusFrequency(BigInt(3200000000L)) ++
|
||||
@@ -140,8 +163,10 @@ class FireSimBoomConfig extends Config(
|
||||
new WithBlockDevice ++
|
||||
new WithBoomL2TLBs(1024) ++
|
||||
new WithoutClockGating ++
|
||||
new WithDefaultMemModel ++
|
||||
new boom.common.WithLargeBooms ++
|
||||
new boom.common.WithNBoomCores(1) ++
|
||||
new WithDefaultFireSimBridges ++
|
||||
new freechips.rocketchip.system.BaseConfig
|
||||
)
|
||||
|
||||
@@ -165,9 +190,6 @@ class FireSimBoomQuadCoreConfig extends Config(
|
||||
//**********************************************************************************
|
||||
//* Supernode Configurations
|
||||
//*********************************************************************************/
|
||||
class WithNumNodes(n: Int) extends Config((pname, site, here) => {
|
||||
case NumNodes => n
|
||||
})
|
||||
|
||||
class SupernodeFireSimRocketChipConfig extends Config(
|
||||
new WithNumNodes(4) ++
|
||||
|
||||
@@ -1,6 +1,7 @@
|
||||
package firesim.firesim
|
||||
|
||||
import chisel3._
|
||||
import chisel3.util.Cat
|
||||
import chisel3.experimental.annotate
|
||||
import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.diplomacy._
|
||||
@@ -11,68 +12,14 @@ import freechips.rocketchip.util._
|
||||
import freechips.rocketchip.tile._
|
||||
import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.rocket.TracedInstruction
|
||||
import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction}
|
||||
import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction}
|
||||
|
||||
import midas.models.AXI4BundleWithEdge
|
||||
import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation}
|
||||
|
||||
import boom.common.BoomTile
|
||||
|
||||
/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges
|
||||
* associated with each port. This drives FASED functional model sizing
|
||||
*/
|
||||
trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem =>
|
||||
val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
|
||||
val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) =>
|
||||
val portName = "axi4"
|
||||
val device = new MemoryDevice
|
||||
|
||||
val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel =>
|
||||
val base = AddressSet.misaligned(memPortParams.base, memPortParams.size)
|
||||
val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes))
|
||||
|
||||
AXI4SlavePortParameters(
|
||||
slaves = Seq(AXI4SlaveParameters(
|
||||
address = base.flatMap(_.intersect(filter)),
|
||||
resources = device.reg,
|
||||
regionType = RegionType.UNCACHED, // cacheable
|
||||
executable = true,
|
||||
supportsWrite = TransferSizes(1, mbus.blockBytes),
|
||||
supportsRead = TransferSizes(1, mbus.blockBytes),
|
||||
interleavedId = Some(0))), // slave does not interleave read responses
|
||||
beatBytes = memPortParams.beatBytes)
|
||||
})
|
||||
|
||||
memAXI4Node := mbus.toDRAMController(Some(portName)) {
|
||||
AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4()
|
||||
}
|
||||
|
||||
memAXI4Node
|
||||
}
|
||||
}
|
||||
|
||||
/** Actually generates the corresponding IO in the concrete Module */
|
||||
trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp {
|
||||
val outer: CanHaveFASEDOptimizedMasterAXI4MemPort
|
||||
|
||||
val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in))))
|
||||
(mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) =>
|
||||
(io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle }
|
||||
}
|
||||
|
||||
def connectSimAXIMem() {
|
||||
(mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) =>
|
||||
(io zip node.in).foreach { case (io, (_, edge)) =>
|
||||
val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size))
|
||||
Module(mem.module).io.axi4.head <> io
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/* Wires out tile trace ports to the top; and wraps them in a Bundle that the
|
||||
* TracerV endpoint can match on.
|
||||
* TracerV bridge can match on.
|
||||
*/
|
||||
object PrintTracePort extends Field[Boolean](false)
|
||||
|
||||
@@ -98,7 +45,7 @@ trait HasTraceIOImp extends LazyModuleImp {
|
||||
// Enabled to test TracerV trace capture
|
||||
if (p(PrintTracePort)) {
|
||||
val traceprint = Wire(UInt(512.W))
|
||||
traceprint := traceIO.asUInt
|
||||
traceprint := Cat(traceIO.traces.map(_.asUInt))
|
||||
printf("TRACEPORT: %x\n", traceprint)
|
||||
}
|
||||
}
|
||||
|
||||
@@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem._
|
||||
import freechips.rocketchip.diplomacy._
|
||||
import freechips.rocketchip.tilelink._
|
||||
import freechips.rocketchip.devices.tilelink._
|
||||
import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp
|
||||
import freechips.rocketchip.config.Parameters
|
||||
import freechips.rocketchip.util.{HeterogeneousBag}
|
||||
import freechips.rocketchip.amba.axi4.AXI4Bundle
|
||||
@@ -13,13 +14,19 @@ import freechips.rocketchip.config.{Field, Parameters}
|
||||
import freechips.rocketchip.diplomacy.LazyModule
|
||||
import utilities.{Subsystem, SubsystemModuleImp}
|
||||
import icenet._
|
||||
import firesim.util.DefaultFireSimHarness
|
||||
import testchipip._
|
||||
import testchipip.SerialAdapter.SERIAL_IF_WIDTH
|
||||
import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp}
|
||||
import sifive.blocks.devices.uart._
|
||||
import midas.models.AXI4BundleWithEdge
|
||||
import java.io.File
|
||||
|
||||
|
||||
object FireSimValName {
|
||||
implicit val valName = ValName("FireSimHarness")
|
||||
}
|
||||
import FireSimValName._
|
||||
|
||||
/*******************************************************************************
|
||||
* Top level DESIGN configurations. These describe the basic instantiations of
|
||||
* the designs being simulated.
|
||||
@@ -31,11 +38,10 @@ import java.io.File
|
||||
* determine which driver to build.
|
||||
*******************************************************************************/
|
||||
|
||||
class FireSim(implicit p: Parameters) extends Subsystem
|
||||
class FireSimDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPort
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial
|
||||
with HasPeripheryUART
|
||||
with HasPeripheryIceNIC
|
||||
@@ -45,11 +51,10 @@ class FireSim(implicit p: Parameters) extends Subsystem
|
||||
override lazy val module = new FireSimModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimModuleImp[+L <: FireSim](l: L) extends SubsystemModuleImp(l)
|
||||
class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripheryIceNICModuleImpValidOnly
|
||||
@@ -57,12 +62,12 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends SubsystemModuleImp(l)
|
||||
with HasTraceIOImp
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
|
||||
|
||||
class FireSimNoNIC(implicit p: Parameters) extends Subsystem
|
||||
class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPort
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial
|
||||
with HasPeripheryUART
|
||||
with HasPeripheryBlockDevice
|
||||
@@ -71,11 +76,10 @@ class FireSimNoNIC(implicit p: Parameters) extends Subsystem
|
||||
override lazy val module = new FireSimNoNICModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends SubsystemModuleImp(l)
|
||||
class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
@@ -83,11 +87,12 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends SubsystemModuleImp
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
|
||||
class FireBoom(implicit p: Parameters) extends Subsystem
|
||||
class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT)
|
||||
|
||||
class FireBoomDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPort
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial
|
||||
with HasPeripheryUART
|
||||
with HasPeripheryIceNIC
|
||||
@@ -97,11 +102,10 @@ class FireBoom(implicit p: Parameters) extends Subsystem
|
||||
override lazy val module = new FireBoomModuleImp(this)
|
||||
}
|
||||
|
||||
class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
|
||||
class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripheryIceNICModuleImpValidOnly
|
||||
@@ -110,11 +114,12 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends SubsystemModuleImp(l)
|
||||
with ExcludeInvalidBoomAssertions
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
|
||||
class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT)
|
||||
|
||||
class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPort
|
||||
with CanHaveMasterAXI4MemPort
|
||||
with HasPeripheryBootROM
|
||||
with HasNoDebug
|
||||
with HasPeripherySerial
|
||||
with HasPeripheryUART
|
||||
with HasPeripheryBlockDevice
|
||||
@@ -123,11 +128,10 @@ class FireBoomNoNIC(implicit p: Parameters) extends Subsystem
|
||||
override lazy val module = new FireBoomNoNICModuleImp(this)
|
||||
}
|
||||
|
||||
class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleImp(l)
|
||||
class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModuleImp(l)
|
||||
with HasRTCModuleImp
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
with HasPeripheryBootROMModuleImp
|
||||
with HasNoDebugModuleImp
|
||||
with HasPeripherySerialModuleImp
|
||||
with HasPeripheryUARTModuleImp
|
||||
with HasPeripheryBlockDeviceModuleImp
|
||||
@@ -135,58 +139,18 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends SubsystemModuleI
|
||||
with ExcludeInvalidBoomAssertions
|
||||
with CanHaveMultiCycleRegfileImp
|
||||
|
||||
case object NumNodes extends Field[Int]
|
||||
|
||||
class SupernodeIO(
|
||||
nNodes: Int,
|
||||
serialWidth: Int,
|
||||
bagPrototype: HeterogeneousBag[AXI4BundleWithEdge])(implicit p: Parameters)
|
||||
extends Bundle {
|
||||
|
||||
val serial = Vec(nNodes, new SerialIO(serialWidth))
|
||||
val mem_axi = Vec(nNodes, bagPrototype.cloneType)
|
||||
val bdev = Vec(nNodes, new BlockDeviceIO)
|
||||
val net = Vec(nNodes, new NICIOvonly)
|
||||
val uart = Vec(nNodes, new UARTPortIO)
|
||||
|
||||
override def cloneType = new SupernodeIO(nNodes, serialWidth, bagPrototype).asInstanceOf[this.type]
|
||||
}
|
||||
|
||||
|
||||
class FireSimSupernode(implicit p: Parameters) extends Module {
|
||||
val nNodes = p(NumNodes)
|
||||
val nodes = Seq.fill(nNodes) {
|
||||
Module(LazyModule(new FireSim).module)
|
||||
}
|
||||
|
||||
val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get))
|
||||
|
||||
io.mem_axi.zip(nodes.map(_.mem_axi4)).foreach {
|
||||
case (out, mem_axi4) => out <> mem_axi4.get
|
||||
}
|
||||
io.serial <> nodes.map(_.serial)
|
||||
io.bdev <> nodes.map(_.bdev)
|
||||
io.net <> nodes.map(_.net)
|
||||
io.uart <> nodes.map(_.uart(0))
|
||||
nodes.foreach{ case n => {
|
||||
n.debug.clockeddmi.get.dmi.req.valid := false.B
|
||||
n.debug.clockeddmi.get.dmi.resp.ready := false.B
|
||||
n.debug.clockeddmi.get.dmiClock := clock
|
||||
n.debug.clockeddmi.get.dmiReset := reset.toBool
|
||||
n.debug.clockeddmi.get.dmi.req.bits.data := DontCare
|
||||
n.debug.clockeddmi.get.dmi.req.bits.addr := DontCare
|
||||
n.debug.clockeddmi.get.dmi.req.bits.op := DontCare
|
||||
} }
|
||||
}
|
||||
class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT)
|
||||
|
||||
class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem
|
||||
with HasHierarchicalBusTopology
|
||||
with HasTraceGenTiles
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPort {
|
||||
with CanHaveMasterAXI4MemPort {
|
||||
override lazy val module = new FireSimTraceGenModuleImp(this)
|
||||
}
|
||||
|
||||
class FireSimTraceGenModuleImp(outer: FireSimTraceGen)
|
||||
extends BaseSubsystemModuleImp(outer)
|
||||
with HasTraceGenTilesModuleImp
|
||||
with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp
|
||||
class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModuleImp(outer)
|
||||
with HasTraceGenTilesModuleImp
|
||||
with CanHaveMasterAXI4MemPortModuleImp
|
||||
|
||||
// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1
|
||||
class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT)
|
||||
|
||||
@@ -23,6 +23,8 @@ abstract class FireSimTestSuite(
|
||||
import scala.concurrent.duration._
|
||||
import ExecutionContext.Implicits.global
|
||||
|
||||
val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs
|
||||
|
||||
lazy val generatorArgs = GeneratorArgs(
|
||||
midasFlowKind = "midas",
|
||||
targetDir = "generated-src",
|
||||
@@ -42,7 +44,6 @@ abstract class FireSimTestSuite(
|
||||
val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}",
|
||||
s"TARGET_CONFIG=${generatorArgs.targetConfigs}",
|
||||
s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}")
|
||||
override lazy val platform = hostParams(midas.Platform)
|
||||
|
||||
def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = {
|
||||
make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"),
|
||||
@@ -112,7 +113,7 @@ abstract class FireSimTestSuite(
|
||||
val resetLength = 51
|
||||
val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}"))
|
||||
val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength)
|
||||
assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length")
|
||||
assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length")
|
||||
assert(verilatedOutput.nonEmpty)
|
||||
for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) {
|
||||
assert(vPrint == sPrint)
|
||||
@@ -122,7 +123,7 @@ abstract class FireSimTestSuite(
|
||||
|
||||
clean
|
||||
mkdirs
|
||||
elaborateAndCompileWithMidas
|
||||
elaborate
|
||||
generateTestSuiteMakefrags
|
||||
runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0"""))
|
||||
diffTracelog("rv64ui-p-simple.out")
|
||||
@@ -130,10 +131,10 @@ abstract class FireSimTestSuite(
|
||||
runSuite("verilator")(FastBlockdevTests)
|
||||
}
|
||||
|
||||
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig")
|
||||
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig")
|
||||
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") {
|
||||
class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config")
|
||||
class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config")
|
||||
class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") {
|
||||
runSuite("verilator")(NICLoopbackTests)
|
||||
}
|
||||
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config")
|
||||
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config")
|
||||
class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams")
|
||||
class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams")
|
||||
|
||||
Submodule generators/sha3 updated: 83dd1955a9...e6f5bab675
24
scripts/build-openocd.sh
Executable file
24
scripts/build-openocd.sh
Executable file
@@ -0,0 +1,24 @@
|
||||
#!/usr/bin/env bash
|
||||
|
||||
# exit script if any command fails
|
||||
set -e
|
||||
set -o pipefail
|
||||
|
||||
RDIR=$(git rev-parse --show-toplevel)
|
||||
|
||||
if [ -z "${RISCV}" ] ; then
|
||||
! [ -r "${RDIR}/env.sh" ] || . "${RDIR}/env.sh"
|
||||
if [ -z "${RISCV}" ] ; then
|
||||
echo "${0}: set the RISCV environment variable to desired install path"
|
||||
exit 1
|
||||
fi
|
||||
fi
|
||||
|
||||
SRCDIR="${RDIR}/toolchains/riscv-tools"
|
||||
. "${RDIR}/scripts/build-util.sh"
|
||||
|
||||
git config --unset submodule.toolchains/riscv-tools/riscv-openocd.update || :
|
||||
module_prepare riscv-openocd
|
||||
module_run riscv-openocd ./bootstrap
|
||||
module_build riscv-openocd --prefix="${RISCV}" \
|
||||
--enable-remote-bitbang --enable-jtag_vpi --disable-werror
|
||||
@@ -1,21 +0,0 @@
|
||||
#!/usr/bin/env bash
|
||||
|
||||
# This ungodly script surreptitiously builds an archive from existing fesvr objects
|
||||
# Invoke from riscv-fesvr/build
|
||||
|
||||
if [ "x$RISCV" = "x" ]
|
||||
then
|
||||
echo "Please set the RISCV environment variable to your preferred install path."
|
||||
exit 1
|
||||
fi
|
||||
|
||||
set -e
|
||||
|
||||
objs=$(make -n -f <(
|
||||
echo 'include Makefile'
|
||||
echo '$(info $(value fesvr_objs))'
|
||||
) | head -n 1)
|
||||
|
||||
ar rcs -o libfesvr.a $objs
|
||||
cp -f libfesvr.a "${RISCV}/lib"
|
||||
|
||||
@@ -6,11 +6,8 @@
|
||||
set -e
|
||||
set -o pipefail
|
||||
|
||||
unamestr=$(uname)
|
||||
RDIR=$(pwd)
|
||||
: ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden
|
||||
|
||||
PRECOMPILED_REPO_HASH=56a40961c98db5e8f904f15dc6efd0870bfefd9e
|
||||
CHIPYARD_DIR="${CHIPYARD_DIR:-$(git rev-parse --show-toplevel)}"
|
||||
|
||||
usage() {
|
||||
echo "usage: ${0} [riscv-tools | esp-tools | ec2fast]"
|
||||
@@ -23,18 +20,13 @@ usage() {
|
||||
error() {
|
||||
echo "${0##*/}: ${1}" >&2
|
||||
}
|
||||
|
||||
#taken from riscv-tools to check for open-ocd autoconf versions
|
||||
check_version() {
|
||||
"$1" --version | awk "NR==1 {if (\$NF>$2) {exit 0} exit 1}" || {
|
||||
error "${3} requires at least ${1} version ${2}"
|
||||
exit 1
|
||||
}
|
||||
die() {
|
||||
error "$1"
|
||||
exit "${2:--1}"
|
||||
}
|
||||
|
||||
TOOLCHAIN="riscv-tools"
|
||||
EC2FASTINSTALL="false"
|
||||
FASTINSTALL="false"
|
||||
|
||||
while getopts 'hH-:' opt ; do
|
||||
case $opt in
|
||||
@@ -64,33 +56,6 @@ elif [ -n "$1" ] ; then
|
||||
TOOLCHAIN="$1"
|
||||
fi
|
||||
|
||||
|
||||
if [ "$EC2FASTINSTALL" = "true" ]; then
|
||||
if [ "$TOOLCHAIN" = "riscv-tools" ]; then
|
||||
cd "$RDIR"
|
||||
git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git
|
||||
cd firesim-riscv-tools-prebuilt
|
||||
git checkout "$PRECOMPILED_REPO_HASH"
|
||||
PREBUILTHASH="$(cat HASH)"
|
||||
git -C "${CHIPYARD_DIR}" submodule update --init "toolchains/${TOOLCHAIN}"
|
||||
cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN"
|
||||
GITHASH="$(git rev-parse HEAD)"
|
||||
cd "$RDIR"
|
||||
echo "prebuilt hash: $PREBUILTHASH"
|
||||
echo "git hash: $GITHASH"
|
||||
if [[ $PREBUILTHASH == $GITHASH && "$EC2FASTINSTALL" == "true" ]]; then
|
||||
FASTINSTALL=true
|
||||
echo "Using fast pre-compiled install for riscv-tools"
|
||||
else
|
||||
error 'error: hash of precompiled toolchain does not match the riscv-tools submodule hash'
|
||||
exit -1
|
||||
fi
|
||||
else
|
||||
error "error: unsupported precompiled toolchain: ${TOOLCHAIN}"
|
||||
exit -1
|
||||
fi
|
||||
fi
|
||||
|
||||
INSTALL_DIR="$TOOLCHAIN-install"
|
||||
|
||||
RISCV="$(pwd)/$INSTALL_DIR"
|
||||
@@ -98,52 +63,67 @@ RISCV="$(pwd)/$INSTALL_DIR"
|
||||
# install risc-v tools
|
||||
export RISCV="$RISCV"
|
||||
|
||||
if [ "$FASTINSTALL" = true ]; then
|
||||
cd firesim-riscv-tools-prebuilt
|
||||
./installrelease.sh
|
||||
mv distrib "$RISCV"
|
||||
# copy HASH in case user wants it later
|
||||
cp HASH "$RISCV"
|
||||
cd "$RDIR"
|
||||
rm -rf firesim-riscv-tools-prebuilt
|
||||
cd "${CHIPYARD_DIR}"
|
||||
|
||||
SRCDIR="$(pwd)/toolchains/${TOOLCHAIN}"
|
||||
[ -d "${SRCDIR}" ] || die "unsupported toolchain: ${TOOLCHAIN}"
|
||||
. ./scripts/build-util.sh
|
||||
|
||||
|
||||
if [ "${EC2FASTINSTALL}" = true ] ; then
|
||||
[ "${TOOLCHAIN}" = 'riscv-tools' ] ||
|
||||
die "unsupported precompiled toolchain: ${TOOLCHAIN}"
|
||||
|
||||
echo '=> Fetching pre-built toolchain'
|
||||
module=toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt
|
||||
git config --unset submodule."${module}".update || :
|
||||
git submodule update --init --depth 1 "${module}"
|
||||
|
||||
echo '==> Verifying toolchain version hash'
|
||||
# Find commit hash without initializing the submodule
|
||||
hashsrc="$(git ls-tree -d HEAD "${SRCDIR}/riscv-gnu-toolchain" | {
|
||||
unset IFS && read -r _ type obj _ &&
|
||||
test -n "${obj}" && test "${type}" = 'commit' && echo "${obj}"
|
||||
}; )" ||
|
||||
die 'failed to obtain riscv-gnu-toolchain submodule hash' "$?"
|
||||
|
||||
read -r hashbin < "${module}/HASH" ||
|
||||
die 'failed to obtain riscv-gnu-toolchain-prebuilt hash' "$?"
|
||||
|
||||
echo "==> ${hashsrc}"
|
||||
[ "${hashsrc}" = "${hashbin}" ] ||
|
||||
die "pre-built version mismatch: ${hashbin}"
|
||||
|
||||
echo '==> Installing pre-built toolchain'
|
||||
"${MAKE}" -C "${module}" DESTDIR="${RISCV}" install
|
||||
git submodule deinit "${module}" || :
|
||||
|
||||
else
|
||||
mkdir -p "$RISCV"
|
||||
git -C "${CHIPYARD_DIR}" submodule update --init --recursive "toolchains/${TOOLCHAIN}" #--jobs 8
|
||||
cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN"
|
||||
|
||||
# Scale number of parallel make jobs by hardware thread count
|
||||
ncpu="$(getconf _NPROCESSORS_ONLN || # GNU
|
||||
getconf NPROCESSORS_ONLN || # *BSD, Solaris
|
||||
nproc --all || # Linux
|
||||
sysctl -n hw.ncpu || # *BSD, OS X
|
||||
:)" 2>/dev/null
|
||||
case ${ncpu} in
|
||||
''|*[^0-9]*) ;; # Ignore non-integer values
|
||||
*) export MAKEFLAGS="-j ${ncpu}" ;;
|
||||
esac
|
||||
|
||||
#build the actual toolchain
|
||||
#./build.sh
|
||||
source build.common
|
||||
echo "Starting RISC-V Toolchain build process"
|
||||
build_project riscv-fesvr --prefix="${RISCV}"
|
||||
build_project riscv-isa-sim --prefix="${RISCV}" --with-fesvr="${RISCV}"
|
||||
build_project riscv-gnu-toolchain --prefix="${RISCV}"
|
||||
CC= CXX= build_project riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf
|
||||
build_project riscv-tests --prefix="${RISCV}/riscv64-unknown-elf"
|
||||
echo -e "\\nRISC-V Toolchain installation completed!"
|
||||
|
||||
# build static libfesvr library for linking into firesim driver (or others)
|
||||
cd riscv-fesvr/build
|
||||
"${CHIPYARD_DIR}/scripts/build-static-libfesvr.sh"
|
||||
cd "$RDIR"
|
||||
# build linux toolchain
|
||||
cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN/riscv-gnu-toolchain/build"
|
||||
make linux
|
||||
echo -e "\\nRISC-V Linux GNU Toolchain installation completed!"
|
||||
"${MAKE}" --version | (
|
||||
read -r makever
|
||||
case ${makever} in
|
||||
'GNU Make '[4-9]\.*|'GNU Make '[1-9][0-9]) ;;
|
||||
*) false ;;
|
||||
esac; ) || die 'obsolete make version; need GNU make 4.x or later'
|
||||
|
||||
module_prepare riscv-gnu-toolchain qemu
|
||||
module_build riscv-gnu-toolchain --prefix="${RISCV}"
|
||||
echo '==> Building GNU/Linux toolchain'
|
||||
module_make riscv-gnu-toolchain linux
|
||||
fi
|
||||
|
||||
module_all riscv-isa-sim --prefix="${RISCV}"
|
||||
# build static libfesvr library for linking into firesim driver (or others)
|
||||
echo '==> Installing libfesvr static library'
|
||||
module_make riscv-isa-sim libfesvr.a
|
||||
cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/"
|
||||
|
||||
CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf
|
||||
module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf"
|
||||
|
||||
# Common tools (not in any particular toolchain dir)
|
||||
SRCDIR="$RDIR/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu
|
||||
|
||||
cd "$RDIR"
|
||||
|
||||
{
|
||||
@@ -153,20 +133,3 @@ cd "$RDIR"
|
||||
echo "export LD_LIBRARY_PATH=\${RISCV}/lib\${LD_LIBRARY_PATH:+":\${LD_LIBRARY_PATH}"}"
|
||||
} > env.sh
|
||||
echo "Toolchain Build Complete!"
|
||||
|
||||
if [ "$FASTINSTALL" = "false" ]; then
|
||||
# commands that can't run on EC2 (specifically, OpenOCD because of autoconf version_
|
||||
# see if the instance info page exists. if not, we are not on ec2.
|
||||
# this is one of the few methods that works without sudo
|
||||
if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then
|
||||
echo "Skipping RISC-V OpenOCD"
|
||||
else
|
||||
echo "Building RISC-V OpenOCD"
|
||||
cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN"
|
||||
check_version automake 1.14 "OpenOCD build"
|
||||
check_version autoconf 2.64 "OpenOCD build"
|
||||
build_project riscv-openocd --prefix="${RISCV}" --enable-remote-bitbang --enable-jtag_vpi --disable-werror
|
||||
echo -e "\\nRISC-V OpenOCD installation completed!"
|
||||
cd "$RDIR"
|
||||
fi
|
||||
fi
|
||||
|
||||
89
scripts/build-util.sh
Normal file
89
scripts/build-util.sh
Normal file
@@ -0,0 +1,89 @@
|
||||
# Derived from
|
||||
# https://github.com/riscv/riscv-tools/blob/master/build.common
|
||||
|
||||
[ -n "${SRCDIR}" ] || exit 1
|
||||
|
||||
# Scale number of parallel make jobs by hardware thread count
|
||||
ncpu="${NPROC:-$(getconf _NPROCESSORS_ONLN || # GNU
|
||||
getconf NPROCESSORS_ONLN || # *BSD, Solaris
|
||||
nproc --all || # Linux
|
||||
sysctl -n hw.ncpu || # *BSD, OS X
|
||||
:)}" 2>/dev/null
|
||||
case ${ncpu} in
|
||||
''|*[!0-9]*) ;; # Ignore non-integer values
|
||||
*) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;;
|
||||
esac
|
||||
|
||||
MAKE=$(command -v gnumake || command -v gmake || command -v make)
|
||||
readonly MAKE
|
||||
|
||||
|
||||
module_prepare() ( # <submodule> [ignored-submodule..]
|
||||
set -e
|
||||
name=$1
|
||||
shift
|
||||
|
||||
dir="${SRCDIR}/${name}"
|
||||
echo "=> Starting ${name} build"
|
||||
echo "==> Initializing ${name} submodule"
|
||||
if [ $# -gt 0 ] ; then
|
||||
git submodule update --init "${dir}"
|
||||
while [ -n "$1" ] ; do
|
||||
git -C "${dir}" config submodule."${1}".update none
|
||||
shift
|
||||
done
|
||||
fi
|
||||
git submodule update --init --recursive "${dir}"
|
||||
)
|
||||
|
||||
module_run() ( # <submodule> <command..>
|
||||
set -e
|
||||
cd "${SRCDIR}/${1}"
|
||||
shift
|
||||
"$@"
|
||||
)
|
||||
|
||||
module_make() ( # <submodule> <target..>
|
||||
set -e -o pipefail
|
||||
cd "${SRCDIR}/${1}/build"
|
||||
shift
|
||||
"${MAKE}" "$@" | tee "build-${1:-make}.log"
|
||||
)
|
||||
|
||||
module_build() ( # <submodule> [configure-arg..]
|
||||
set -e -o pipefail
|
||||
name=$1
|
||||
shift
|
||||
|
||||
cd "${SRCDIR}/${name}"
|
||||
|
||||
if [ -e build ] ; then
|
||||
echo "==> Removing existing ${name}/build directory"
|
||||
rm -rf build
|
||||
fi
|
||||
if ! [ -e configure ] ; then
|
||||
echo "==> Updating autoconf files for ${name}"
|
||||
find . -iname configure.ac -type f -print0 |
|
||||
while read -r -d '' file ; do
|
||||
mkdir -p -- "${file%/*}/m4"
|
||||
done
|
||||
autoreconf -i
|
||||
fi
|
||||
|
||||
mkdir -p build
|
||||
cd build
|
||||
{
|
||||
export PATH="${RISCV:+${RISCV}/bin:}${PATH}"
|
||||
echo "==> Configuring ${name}"
|
||||
../configure "$@"
|
||||
echo "==> Building ${name}"
|
||||
"${MAKE}"
|
||||
echo "==> Installing ${name}"
|
||||
"${MAKE}" install
|
||||
} 2>&1 | tee build.log
|
||||
)
|
||||
|
||||
module_all() { # <submodule> [configure-arg..]
|
||||
module_prepare "$1"
|
||||
module_build "$@"
|
||||
}
|
||||
@@ -4,16 +4,34 @@
|
||||
set -e
|
||||
set -o pipefail
|
||||
|
||||
unamestr=$(uname)
|
||||
RDIR=$(pwd)
|
||||
scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
|
||||
RDIR=$(git rev-parse --show-toplevel)
|
||||
|
||||
_usage() {
|
||||
echo "usage: ${0} [--no-firesim]" >&2
|
||||
exit 1
|
||||
}
|
||||
|
||||
NO_FIRESIM=false
|
||||
while getopts 'h-:' opt ; do
|
||||
case ${opt} in
|
||||
-)
|
||||
case ${OPTARG} in
|
||||
no-firesim) NO_FIRESIM=true ;;
|
||||
*) echo "invalid option: --${OPTARG}" >&2 ; _usage ;;
|
||||
esac ;;
|
||||
h) _usage ;;
|
||||
*) echo "invalid option: -${opt}" >&2 ; _usage ;;
|
||||
esac
|
||||
done
|
||||
shift $((OPTIND - 1))
|
||||
|
||||
# Ignore toolchain submodules
|
||||
cd "$RDIR"
|
||||
for name in toolchains/*/*/ ; do
|
||||
git config submodule."${name%/}".update none
|
||||
done
|
||||
git config submodule.toolchains/qemu.update none
|
||||
|
||||
# ignore riscv-tools for submodule init recursive
|
||||
# you must do this globally (otherwise riscv-tools deep
|
||||
# in the submodule tree will get pulled anyway
|
||||
git config submodule.toolchains/riscv-tools.update none
|
||||
git config submodule.toolchains/esp-tools.update none
|
||||
git config --global submodule.experimental-blocks.update none
|
||||
# Disable updates to the FireSim submodule until explicitly requested
|
||||
git config submodule.sims/firesim.update none
|
||||
# Disable updates to the hammer tool plugins repos
|
||||
@@ -21,20 +39,23 @@ git config submodule.vlsi/hammer-cadence-plugins.update none
|
||||
git config submodule.vlsi/hammer-synopsys-plugins.update none
|
||||
git config submodule.vlsi/hammer-mentor-plugins.update none
|
||||
git submodule update --init --recursive #--jobs 8
|
||||
# unignore riscv-tools,catapult-shell2 globally
|
||||
git config --unset submodule.toolchains/riscv-tools.update
|
||||
git config --unset submodule.toolchains/esp-tools.update
|
||||
git config --global --unset submodule.experimental-blocks.update
|
||||
# Un-ignore toolchain submodules
|
||||
for name in toolchains/*/*/ ; do
|
||||
git config --unset submodule."${name%/}".update
|
||||
done
|
||||
git config --unset submodule.toolchains/qemu.update
|
||||
|
||||
git config --unset submodule.vlsi/hammer-cadence-plugins.update
|
||||
git config --unset submodule.vlsi/hammer-synopsys-plugins.update
|
||||
git config --unset submodule.vlsi/hammer-mentor-plugins.update
|
||||
|
||||
# Renable firesim and init only the required submodules to provide
|
||||
# all required scala deps, without doing a full build-setup
|
||||
git config --unset submodule.sims/firesim.update
|
||||
cd "${scripts_dir}/../sims"
|
||||
git submodule update --init firesim
|
||||
cd firesim/sim
|
||||
git submodule update --init midas
|
||||
cd "$RDIR"
|
||||
git config submodule.sims/firesim.update none
|
||||
if [ $NO_FIRESIM = false ]; then
|
||||
echo "initializing firesim"
|
||||
# Renable firesim and init only the required submodules to provide
|
||||
# all required scala deps, without doing a full build-setup
|
||||
git config --unset submodule.sims/firesim.update
|
||||
git submodule update --init sims/firesim
|
||||
git -C sims/firesim submodule update --init sim/midas
|
||||
git -C sims/firesim submodule update --init --recursive sw/firesim-software
|
||||
git config submodule.sims/firesim.update none
|
||||
fi
|
||||
|
||||
Submodule sims/firesim updated: 92fe0e4def...afd51ab7a8
@@ -48,8 +48,7 @@ VCS_CC_OPTS = \
|
||||
-CC "-I$(VCS_HOME)/include" \
|
||||
-CC "-I$(RISCV)/include" \
|
||||
-CC "-std=c++11" \
|
||||
-CC "-Wl,-rpath,$(RISCV)/lib" \
|
||||
$(RISCV)/lib/libfesvr.so
|
||||
$(RISCV)/lib/libfesvr.a
|
||||
|
||||
VCS_NONCC_OPTS = \
|
||||
+lint=all,noVCDE,noONGS,noUI \
|
||||
|
||||
1
software/firemarshal
Symbolic link
1
software/firemarshal
Symbolic link
@@ -0,0 +1 @@
|
||||
../sims/firesim/sw/firesim-software/
|
||||
Submodule toolchains/esp-tools deleted from dcb6012f77
1
toolchains/esp-tools/riscv-gnu-toolchain
Submodule
1
toolchains/esp-tools/riscv-gnu-toolchain
Submodule
Submodule toolchains/esp-tools/riscv-gnu-toolchain added at 9f53229398
1
toolchains/esp-tools/riscv-isa-sim
Submodule
1
toolchains/esp-tools/riscv-isa-sim
Submodule
Submodule toolchains/esp-tools/riscv-isa-sim added at 0ffa02e5b4
1
toolchains/esp-tools/riscv-pk
Submodule
1
toolchains/esp-tools/riscv-pk
Submodule
Submodule toolchains/esp-tools/riscv-pk added at a3e4ac61d2
1
toolchains/esp-tools/riscv-tests
Submodule
1
toolchains/esp-tools/riscv-tests
Submodule
Submodule toolchains/esp-tools/riscv-tests added at f1370d0543
1
toolchains/qemu
Submodule
1
toolchains/qemu
Submodule
Submodule toolchains/qemu added at 4f59102571
Submodule toolchains/riscv-tools deleted from bce7b5e363
1
toolchains/riscv-tools/riscv-gnu-toolchain
Submodule
1
toolchains/riscv-tools/riscv-gnu-toolchain
Submodule
Submodule toolchains/riscv-tools/riscv-gnu-toolchain added at 2855d823a6
Submodule toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt added at 5e32a0157f
1
toolchains/riscv-tools/riscv-isa-sim
Submodule
1
toolchains/riscv-tools/riscv-isa-sim
Submodule
Submodule toolchains/riscv-tools/riscv-isa-sim added at 9443c1dbac
1
toolchains/riscv-tools/riscv-openocd
Submodule
1
toolchains/riscv-tools/riscv-openocd
Submodule
Submodule toolchains/riscv-tools/riscv-openocd added at 7c82a7b9d5
1
toolchains/riscv-tools/riscv-pk
Submodule
1
toolchains/riscv-tools/riscv-pk
Submodule
Submodule toolchains/riscv-tools/riscv-pk added at a3e4ac61d2
1
toolchains/riscv-tools/riscv-tests
Submodule
1
toolchains/riscv-tools/riscv-tests
Submodule
Submodule toolchains/riscv-tools/riscv-tests added at 249796cec9
@@ -24,21 +24,25 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool:
|
||||
x.append('''
|
||||
# TODO
|
||||
# Place custom TCL here
|
||||
set_db route_design_bottom_routing_layer 2
|
||||
set_db route_design_top_routing_layer 7
|
||||
''')
|
||||
return True
|
||||
|
||||
def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool:
|
||||
"""
|
||||
Scale the final GDS by a factor of 4
|
||||
hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script
|
||||
"""
|
||||
x.append('''
|
||||
# Write script out to a temporary file and execute it
|
||||
set fp [open "{script_file}" "w"]
|
||||
puts -nonewline $fp "{script_text}"
|
||||
close $fp
|
||||
if {{ [catch {{ exec python3 {script_file} }} msg] }} {{
|
||||
puts "$::errorInfo"
|
||||
}}
|
||||
|
||||
# Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python
|
||||
set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"]
|
||||
python3 {script_file}
|
||||
'''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py")))
|
||||
return True
|
||||
|
||||
@@ -50,16 +54,21 @@ class ExampleDriver(CLIDriver):
|
||||
# Default set of steps can be found in the CAD tool plugin's __init__.py
|
||||
|
||||
# make_pre_insertion_hook will execute the custom hook before the specified step
|
||||
hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
|
||||
# SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK)
|
||||
# hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers),
|
||||
|
||||
# make_post_insertion_hook will execute the custom hook after the specified step
|
||||
hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings),
|
||||
|
||||
# make_replacement_hook will replace the specified step with a custom hook
|
||||
hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
|
||||
# hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells),
|
||||
|
||||
# make_removal_hook will remove the specified step from the flow
|
||||
hammer_vlsi.HammerTool.make_removal_hook("place_bumps"),
|
||||
|
||||
# The target step in any of the above calls may be a default step or another one of your custom hooks
|
||||
|
||||
# This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py)
|
||||
# This is an example of a technology-supplied hook
|
||||
hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds)
|
||||
]
|
||||
return extra_hooks
|
||||
|
||||
@@ -34,8 +34,11 @@ par.generate_power_straps_options:
|
||||
- M7
|
||||
- M8
|
||||
- M9
|
||||
track_width: 5
|
||||
pin_layers:
|
||||
- M9
|
||||
track_width: 7 # minimum allowed for M2 & M3
|
||||
track_spacing: 0
|
||||
track_spacing_M3: 1 # to avoid M2 shorts at higher density
|
||||
track_start: 10
|
||||
power_utilization: 0.05
|
||||
power_utilization_M8: 1.0
|
||||
@@ -54,7 +57,7 @@ vlsi.inputs.placement_constraints:
|
||||
left: 0
|
||||
right: 0
|
||||
top: 0
|
||||
bottom: 1.08 #must be at least this number
|
||||
bottom: 0
|
||||
- path: "Sha3AccelwBB/dco"
|
||||
type: hardmacro
|
||||
x: 108
|
||||
@@ -63,6 +66,13 @@ vlsi.inputs.placement_constraints:
|
||||
height: 128
|
||||
orientation: r0
|
||||
top_layer: M9
|
||||
- path: "Sha3AccelwBB/place_obs_bottom"
|
||||
type: obstruction
|
||||
obs_types: ["place"]
|
||||
x: 0
|
||||
y: 0
|
||||
width: 300
|
||||
height: 1.08 # 1 core site tall, necessary to avoid shorts
|
||||
|
||||
# Pin placement constraints
|
||||
vlsi.inputs.pin_mode: generated
|
||||
@@ -124,7 +134,7 @@ synthesis.genus.version: "1813"
|
||||
vlsi.core.par_tool: "innovus"
|
||||
vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"]
|
||||
vlsi.core.par_tool_path_meta: "append"
|
||||
par.innovus.version: "191"
|
||||
par.innovus.version: "181"
|
||||
par.innovus.design_flow_effort: "standard"
|
||||
par.inputs.gds_merge: true
|
||||
# Calibre options
|
||||
|
||||
Binary file not shown.
@@ -6,14 +6,14 @@ MACRO ExampleDCO
|
||||
CLASS BLOCK ;
|
||||
ORIGIN 0 0 ;
|
||||
FOREIGN ExampleDCO 0 0 ;
|
||||
SIZE 128.0 BY 128.0 ;
|
||||
SIZE 123.936 BY 125.536 ;
|
||||
SYMMETRY X Y ;
|
||||
PIN VDD
|
||||
DIRECTION INOUT ;
|
||||
USE POWER ;
|
||||
PORT
|
||||
LAYER M7 ;
|
||||
RECT 32.96 124.0 33.6 128.0 ;
|
||||
LAYER M5 ;
|
||||
RECT 3.024 121.536 3.8 125.536 ;
|
||||
END
|
||||
END VDD
|
||||
PIN VSS
|
||||
@@ -21,327 +21,327 @@ MACRO ExampleDCO
|
||||
USE GROUND ;
|
||||
PORT
|
||||
LAYER M5 ;
|
||||
RECT 93.12 124.0 93.76 128.0 ;
|
||||
RECT 1.728 121.536 2.5 125.536 ;
|
||||
END
|
||||
END VSS
|
||||
PIN col_sel_b[13]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 113.28 4.0 113.664 ;
|
||||
END
|
||||
END col_sel_b[13]
|
||||
PIN col_sel_b[11]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 107.648 4.0 108.032 ;
|
||||
END
|
||||
END col_sel_b[11]
|
||||
PIN col_sel_b[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 90.752 4.0 91.136 ;
|
||||
END
|
||||
END col_sel_b[5]
|
||||
PIN col_sel_b[12]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 110.464 4.0 110.848 ;
|
||||
END
|
||||
END col_sel_b[12]
|
||||
PIN col_sel_b[10]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 104.832 4.0 105.216 ;
|
||||
END
|
||||
END col_sel_b[10]
|
||||
PIN col_sel_b[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 102.016 4.0 102.4 ;
|
||||
END
|
||||
END col_sel_b[9]
|
||||
PIN col_sel_b[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 99.2 4.0 99.584 ;
|
||||
END
|
||||
END col_sel_b[8]
|
||||
PIN col_sel_b[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 96.384 4.0 96.768 ;
|
||||
END
|
||||
END col_sel_b[7]
|
||||
PIN col_sel_b[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 93.568 4.0 93.952 ;
|
||||
END
|
||||
END col_sel_b[6]
|
||||
PIN col_sel_b[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 87.936 4.0 88.32 ;
|
||||
END
|
||||
END col_sel_b[4]
|
||||
PIN col_sel_b[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 85.12 4.0 85.504 ;
|
||||
END
|
||||
END col_sel_b[3]
|
||||
PIN col_sel_b[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 82.304 4.0 82.688 ;
|
||||
END
|
||||
END col_sel_b[2]
|
||||
PIN col_sel_b[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 79.488 4.0 79.872 ;
|
||||
END
|
||||
END col_sel_b[1]
|
||||
PIN col_sel_b[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 76.672 4.0 77.056 ;
|
||||
END
|
||||
END col_sel_b[0]
|
||||
PIN row_sel_b[14]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 71.04 4.0 71.424 ;
|
||||
END
|
||||
END row_sel_b[14]
|
||||
PIN row_sel_b[13]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 68.224 4.0 68.608 ;
|
||||
END
|
||||
END row_sel_b[13]
|
||||
PIN row_sel_b[12]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 65.408 4.0 65.792 ;
|
||||
END
|
||||
END row_sel_b[12]
|
||||
PIN row_sel_b[11]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 62.592 4.0 62.976 ;
|
||||
END
|
||||
END row_sel_b[11]
|
||||
PIN row_sel_b[10]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 59.776 4.0 60.16 ;
|
||||
END
|
||||
END row_sel_b[10]
|
||||
PIN row_sel_b[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 56.96 4.0 57.344 ;
|
||||
END
|
||||
END row_sel_b[9]
|
||||
PIN row_sel_b[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 54.144 4.0 54.528 ;
|
||||
END
|
||||
END row_sel_b[8]
|
||||
PIN row_sel_b[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 51.328 4.0 51.712 ;
|
||||
END
|
||||
END row_sel_b[7]
|
||||
PIN row_sel_b[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 48.512 4.0 48.896 ;
|
||||
END
|
||||
END row_sel_b[6]
|
||||
PIN row_sel_b[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 45.696 4.0 46.08 ;
|
||||
END
|
||||
END row_sel_b[5]
|
||||
PIN row_sel_b[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 42.88 4.0 43.264 ;
|
||||
END
|
||||
END row_sel_b[4]
|
||||
PIN row_sel_b[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 40.064 4.0 40.448 ;
|
||||
END
|
||||
END row_sel_b[3]
|
||||
PIN row_sel_b[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 37.248 4.0 37.632 ;
|
||||
END
|
||||
END row_sel_b[2]
|
||||
PIN row_sel_b[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 34.432 4.0 34.816 ;
|
||||
END
|
||||
END row_sel_b[1]
|
||||
PIN row_sel_b[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 31.616 4.0 32.0 ;
|
||||
END
|
||||
END row_sel_b[0]
|
||||
PIN code_regulator[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 28.8 4.0 29.184 ;
|
||||
END
|
||||
END code_regulator[7]
|
||||
PIN code_regulator[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 25.984 4.0 26.368 ;
|
||||
END
|
||||
END code_regulator[6]
|
||||
PIN code_regulator[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 23.168 4.0 23.552 ;
|
||||
END
|
||||
END code_regulator[5]
|
||||
PIN code_regulator[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 20.352 4.0 20.736 ;
|
||||
END
|
||||
END code_regulator[4]
|
||||
PIN code_regulator[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 17.536 4.0 17.92 ;
|
||||
END
|
||||
END code_regulator[3]
|
||||
PIN code_regulator[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 14.72 4.0 15.104 ;
|
||||
END
|
||||
END code_regulator[2]
|
||||
PIN code_regulator[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 11.904 4.0 12.288 ;
|
||||
END
|
||||
END code_regulator[1]
|
||||
PIN code_regulator[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 9.088 4.0 9.472 ;
|
||||
END
|
||||
END code_regulator[0]
|
||||
PIN row_sel_b[15]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 73.856 4.0 74.24 ;
|
||||
END
|
||||
END row_sel_b[15]
|
||||
PIN dither
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 6.272 4.0 6.656 ;
|
||||
RECT 0.0 0.384 1.2 0.768 ;
|
||||
END
|
||||
END dither
|
||||
PIN row_sel_b[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 1.536 1.2 1.92 ;
|
||||
END
|
||||
END row_sel_b[0]
|
||||
PIN row_sel_b[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 2.688 1.2 3.072 ;
|
||||
END
|
||||
END row_sel_b[1]
|
||||
PIN row_sel_b[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 3.84 1.2 4.224 ;
|
||||
END
|
||||
END row_sel_b[2]
|
||||
PIN row_sel_b[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 4.992 1.2 5.376 ;
|
||||
END
|
||||
END row_sel_b[3]
|
||||
PIN row_sel_b[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 6.144 1.2 6.528 ;
|
||||
END
|
||||
END row_sel_b[4]
|
||||
PIN row_sel_b[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 7.296 1.2 7.68 ;
|
||||
END
|
||||
END row_sel_b[5]
|
||||
PIN row_sel_b[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 8.448 1.2 8.832 ;
|
||||
END
|
||||
END row_sel_b[6]
|
||||
PIN row_sel_b[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 9.6 1.2 9.984 ;
|
||||
END
|
||||
END row_sel_b[7]
|
||||
PIN row_sel_b[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 10.752 1.2 11.136 ;
|
||||
END
|
||||
END row_sel_b[8]
|
||||
PIN row_sel_b[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 11.904 1.2 12.288 ;
|
||||
END
|
||||
END row_sel_b[9]
|
||||
PIN row_sel_b[10]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 13.056 1.2 13.44 ;
|
||||
END
|
||||
END row_sel_b[10]
|
||||
PIN row_sel_b[11]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 14.208 1.2 14.592 ;
|
||||
END
|
||||
END row_sel_b[11]
|
||||
PIN row_sel_b[12]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 15.36 1.2 15.744 ;
|
||||
END
|
||||
END row_sel_b[12]
|
||||
PIN row_sel_b[13]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 16.512 1.2 16.896 ;
|
||||
END
|
||||
END row_sel_b[13]
|
||||
PIN row_sel_b[14]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 17.664 1.2 18.048 ;
|
||||
END
|
||||
END row_sel_b[14]
|
||||
PIN row_sel_b[15]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 18.816 1.2 19.2 ;
|
||||
END
|
||||
END row_sel_b[15]
|
||||
PIN col_sel_b[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 19.968 1.2 20.352 ;
|
||||
END
|
||||
END col_sel_b[0]
|
||||
PIN col_sel_b[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 21.12 1.2 21.504 ;
|
||||
END
|
||||
END col_sel_b[1]
|
||||
PIN col_sel_b[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 22.272 1.2 22.656 ;
|
||||
END
|
||||
END col_sel_b[2]
|
||||
PIN col_sel_b[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 23.424 1.2 23.808 ;
|
||||
END
|
||||
END col_sel_b[3]
|
||||
PIN col_sel_b[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 24.576 1.2 24.96 ;
|
||||
END
|
||||
END col_sel_b[4]
|
||||
PIN col_sel_b[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 25.728 1.2 26.112 ;
|
||||
END
|
||||
END col_sel_b[5]
|
||||
PIN col_sel_b[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 26.88 1.2 27.264 ;
|
||||
END
|
||||
END col_sel_b[6]
|
||||
PIN col_sel_b[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 28.032 1.2 28.416 ;
|
||||
END
|
||||
END col_sel_b[7]
|
||||
PIN col_sel_b[8]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 29.184 1.2 29.568 ;
|
||||
END
|
||||
END col_sel_b[8]
|
||||
PIN col_sel_b[9]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 30.336 1.2 30.72 ;
|
||||
END
|
||||
END col_sel_b[9]
|
||||
PIN col_sel_b[10]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 31.488 1.2 31.872 ;
|
||||
END
|
||||
END col_sel_b[10]
|
||||
PIN col_sel_b[11]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 32.64 1.2 33.024 ;
|
||||
END
|
||||
END col_sel_b[11]
|
||||
PIN col_sel_b[12]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 33.792 1.2 34.176 ;
|
||||
END
|
||||
END col_sel_b[12]
|
||||
PIN col_sel_b[13]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 34.944 1.2 35.328 ;
|
||||
END
|
||||
END col_sel_b[13]
|
||||
PIN code_regulator[0]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 36.096 1.2 36.48 ;
|
||||
END
|
||||
END code_regulator[0]
|
||||
PIN code_regulator[1]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 37.248 1.2 37.632 ;
|
||||
END
|
||||
END code_regulator[1]
|
||||
PIN code_regulator[2]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 38.4 1.2 38.784 ;
|
||||
END
|
||||
END code_regulator[2]
|
||||
PIN code_regulator[3]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 39.552 1.2 39.936 ;
|
||||
END
|
||||
END code_regulator[3]
|
||||
PIN code_regulator[4]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 40.704 1.2 41.088 ;
|
||||
END
|
||||
END code_regulator[4]
|
||||
PIN code_regulator[5]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 41.856 1.2 42.24 ;
|
||||
END
|
||||
END code_regulator[5]
|
||||
PIN code_regulator[6]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 43.008 1.2 43.392 ;
|
||||
END
|
||||
END code_regulator[6]
|
||||
PIN code_regulator[7]
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 0.0 44.16 1.2 44.544 ;
|
||||
END
|
||||
END code_regulator[7]
|
||||
PIN sleep_b
|
||||
DIRECTION INPUT ;
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M5 ;
|
||||
RECT 9.792 0.0 10.176 4.0 ;
|
||||
LAYER M4 ;
|
||||
RECT 0.0 45.312 1.2 45.696 ;
|
||||
END
|
||||
END sleep_b
|
||||
PIN clock
|
||||
@@ -349,30 +349,28 @@ MACRO ExampleDCO
|
||||
USE SIGNAL ;
|
||||
PORT
|
||||
LAYER M4 ;
|
||||
RECT 124.0 70.864 128.0 71.248 ;
|
||||
RECT 122.736 0.384 123.936 0.768 ;
|
||||
END
|
||||
END clock
|
||||
OBS
|
||||
LAYER M1 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M2 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M3 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M4 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M5 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M6 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M7 ;
|
||||
RECT 4.0 4.0 124.0 124.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M8 ;
|
||||
RECT 0.0 0.0 128.0 128.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
LAYER M9 ;
|
||||
RECT 0.0 0.0 128.0 128.0 ;
|
||||
LAYER Pad ;
|
||||
RECT 0.0 0.0 128.0 128.0 ;
|
||||
RECT 1.2 0.0 122.736 121.536 ;
|
||||
END
|
||||
END ExampleDCO
|
||||
|
||||
|
||||
Submodule vlsi/hammer updated: 1b07b9a378...5c0909ebd6
Submodule vlsi/hammer-cadence-plugins updated: 06ce365b36...5f5d9d9e57
66
vlsi/view_gds.py
Executable file
66
vlsi/view_gds.py
Executable file
@@ -0,0 +1,66 @@
|
||||
import sys
|
||||
|
||||
try:
|
||||
import gdspy
|
||||
except ImportError:
|
||||
print('Bad gdspy installation!')
|
||||
sys.exit()
|
||||
|
||||
print('Loading GDS...')
|
||||
gds_lib = gdspy.GdsLibrary().read_gds(infile=str(sys.argv[1]), units='import')
|
||||
|
||||
# Comment to show layer
|
||||
hidden=[
|
||||
(1, 0), #well
|
||||
(1, 251), #well lbl
|
||||
(2, 0), #fin
|
||||
(3, 0), #psub
|
||||
(3, 251), #psub lbl
|
||||
(7, 0), #gate
|
||||
(8, 0), #dummy
|
||||
(10, 0), #gate cut
|
||||
(11, 0), #active
|
||||
(12, 0), #nselect
|
||||
(13, 0), #pselect
|
||||
(16, 0), #LIG
|
||||
(17, 0), #LISD
|
||||
(18, 0), #V0
|
||||
(19, 0), #M1
|
||||
(19, 251), #M1 lbl
|
||||
(21, 0), #V1
|
||||
#(20, 0), #M2
|
||||
(20, 251), #M2 lbl
|
||||
#(25, 0), #V2
|
||||
#(30, 0), #M3
|
||||
(30, 251), #M3 lbl
|
||||
#(35, 0), #V3
|
||||
#(40, 0), #M4
|
||||
(40, 251), #M4 lbl
|
||||
(45, 0), #V4
|
||||
(50, 0), #M5
|
||||
(50, 251), #M5 lbl
|
||||
(55, 0), #V5
|
||||
(60, 0), #M6
|
||||
(60, 251), #M6 lbl
|
||||
(65, 0), #V6
|
||||
(70, 0), #M7
|
||||
(70, 251), #M7 lbl
|
||||
(75, 0), #V7
|
||||
(80, 0), #M8
|
||||
(80, 251), #M8 lbl
|
||||
(85, 0), #V8
|
||||
(88, 0), #SDT
|
||||
(90, 0), #M9
|
||||
(90, 251), #M9 lbl
|
||||
(95, 0), #V9
|
||||
(96, 0), #Pad
|
||||
(97, 0), #SLVT
|
||||
(98, 0), #LVT
|
||||
(99, 0), #SRAMDRC
|
||||
(100, 0), #???
|
||||
(101, 0), #???
|
||||
(110, 0) #SRAMVT
|
||||
]
|
||||
|
||||
print('Opening layout...')
|
||||
gdspy.LayoutViewer(gds_lib, hidden_types=hidden, depth=1)
|
||||
Reference in New Issue
Block a user