From 270e558272cd46a37748e79b928e9c76b83e67e9 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 23 Jul 2019 22:04:12 +0000 Subject: [PATCH 01/61] Initial MIDAS2 support --- .../firechip/src/main/scala/SimConfigs.scala | 4 ++ .../src/main/scala/TargetMixins.scala | 50 ++++++++++++++++++- .../firechip/src/main/scala/Targets.scala | 12 +++-- .../src/test/scala/ScalaTestSuite.scala | 7 +-- sims/firesim | 2 +- 5 files changed, 66 insertions(+), 9 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 1118fe07..937c2877 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -52,3 +52,7 @@ class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) +class Midas2Config extends Config( + new WithMultiCycleRamModels ++ + new FireSimConfig) + diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 7b4d5d4f..535e354a 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -1,6 +1,7 @@ package firesim.firesim import chisel3._ +import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ @@ -12,7 +13,31 @@ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.models.AXI4BundleWithEdge -import midas.targetutils.ExcludeInstanceAsserts +import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} + +/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ +trait HasDefaultBusConfiguration { + this: BaseSubsystem => + // The sbus masters the cbus; here we convert TL-UH -> TL-UL + sbus.crossToBus(cbus, NoCrossing) + + // The cbus masters the pbus; which might be clocked slower + cbus.crossToBus(pbus, SynchronousCrossing()) + + // The fbus masters the sbus; both are TL-UH or TL-C + FlipRendering { implicit p => + sbus.crossFromBus(fbus, SynchronousCrossing()) + } + + // The sbus masters the mbus; here we convert TL-C -> TL-UH + private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) + private val (in, out, halt) = coherenceManager(this) + if (nBanks != 0) { + sbus.coupleTo("coherence_manager") { in :*= _ } + mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } + } +} + /** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges * associated with each port. This drives FASED functional model sizing @@ -104,3 +129,26 @@ trait ExcludeInvalidBoomAssertions extends LazyModuleImp { ExcludeInstanceAsserts(("NonBlockingDCache", "dtlb")) } +trait CanHaveBoomMultiCycleRegfileImp { + val outer: boom.system.BoomRocketSubsystem + val cores = outer.boomTiles.map(tile => tile.module.core) + cores.foreach({ core => + core.iregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + if (core.fp_pipeline != null) core.fp_pipeline.fregfile match { + case irf: boom.exu.RegisterFileSynthesizable => annotate(MemModelAnnotation(irf.regfile)) + case _ => Nil + } + + }) +} +trait CanHaveRocketMultiCycleRegfileImp { + val outer: RocketSubsystem + outer.rocketTiles.foreach({ tile => + annotate(MemModelAnnotation(tile.module.core.rocketImpl.rf.rf)) + tile.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile))) + }) +} diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 7f8bb830..34477509 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -31,7 +31,7 @@ import java.io.File *******************************************************************************/ class FireSim(implicit p: Parameters) extends RocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -54,10 +54,11 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasPeripheryIceNICModuleImpValidOnly with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -78,10 +79,11 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp + with CanHaveRocketMultiCycleRegfileImp class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -105,9 +107,10 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem - with HasHierarchicalBusTopology + with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM with HasNoDebug @@ -129,6 +132,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys with HasPeripheryBlockDeviceModuleImp with HasTraceIOImp with ExcludeInvalidBoomAssertions + with CanHaveBoomMultiCycleRegfileImp case object NumNodes extends Field[Int] diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 54848ac8..44c4bff0 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,9 +109,9 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 50 + val resetLength = 51 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) - val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength + 1) + val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { @@ -131,8 +131,9 @@ abstract class FireSimTestSuite( } class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") -class RocketF1ClockDivTests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimClockDivConfig") class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { runSuite("verilator")(NICLoopbackTests) } +class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config") +class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config") diff --git a/sims/firesim b/sims/firesim index 4cd75833..a3d48a43 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4cd75833dfc1f9f796a1c5505ece6937fd253189 +Subproject commit a3d48a43a972e663e45a2ce4617a798a940d6a2b From a146d0040d4112c4b4fbe253b235481d546b4337 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 19 Aug 2019 11:15:07 -0700 Subject: [PATCH 02/61] [firechip] Add MIDAS environments for all targets --- .../firechip/src/main/scala/SimConfigs.scala | 16 +-------- .../src/main/scala/TargetConfigs.scala | 36 +++++++++++++++++-- .../firechip/src/main/scala/Targets.scala | 34 ++++++++++++------ 3 files changed, 59 insertions(+), 27 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 937c2877..6f6464dc 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -19,40 +19,26 @@ import firesim.configs._ * reconstruct what is in a particular AGFI. These tags are also used to * determine which driver to build. *******************************************************************************/ -class FireSimConfig extends Config( - new WithSerialWidget ++ - new WithUARTWidget ++ - new WithSimpleNICWidget ++ - new WithBlockDevWidget ++ - new WithDefaultMemModel ++ - new WithTracerVWidget ++ - new BasePlatformConfig) +class FireSimConfig extends Config(new BasePlatformConfig) class FireSimClockDivConfig extends Config( - new WithDefaultMemModel(clockDivision = 2) ++ new FireSimConfig) class FireSimDDR3Config extends Config( - new FCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3LLC4MBConfig extends Config( - new FCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSConfig extends Config( - new FRFCFS16GBQuadRank ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB ++ new FireSimConfig) class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( - new FRFCFS16GBQuadRankLLC4MB3Div ++ new FireSimConfig) class Midas2Config extends Config( new WithMultiCycleRamModels ++ new FireSimConfig) - diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9be95d89..531c067a 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -10,10 +10,14 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.debug.DebugModuleParams import boom.system.BoomTilesKey -import testchipip.{WithBlockDevice, BlockDeviceKey, BlockDeviceConfig} +import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import icenet._ +import firesim.util.{EndpointKey, TieOffDebug} +import firesim.endpoints._ +import firesim.configs.WithDefaultMemModel + class WithBootROM extends Config((site, here, up) => { case BootROMParams => { val chipyardBootROM = new File(s"./generators/testchipip/bootrom/bootrom.rv${site(XLen)}.img") @@ -33,13 +37,33 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => }) class WithUARTKey extends Config((site, here, up) => { - case PeripheryUARTKey => List(UARTParams( + case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint) + case PeripheryUARTKey => List(UARTParams( address = BigInt(0x54000000L), nTxEntries = 256, nRxEntries = 256)) }) +class WithSerialEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint) +}) + +class WithTracerVEndpoint extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint) +}) + +class WithBlockDevice extends Config( + new Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher) + }) ++ new testchipip.WithBlockDevice +) + +class WithTieOffDebug extends Config((site, here, up) => { + case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug) +}) + class WithNICKey extends Config((site, here, up) => { + //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint) case NICKey => NICConfig( inBufFlits = 8192, ctrlQueueDepth = 64) @@ -97,6 +121,10 @@ class FireSimRocketChipConfig extends Config( new WithRocketL2TLBs(1024) ++ new WithPerfCounters ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -136,6 +164,10 @@ class FireSimBoomConfig extends Config( new WithBlockDevice ++ new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ + new WithDefaultMemModel ++ + new WithSerialEndpoint ++ + new WithTracerVEndpoint ++ + new WithTieOffDebug ++ // Using a small config because it has 64-bit system bus, and compiles quickly new boom.system.SmallBoomConfig) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 34477509..e592f5d1 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -17,8 +17,14 @@ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import sifive.blocks.devices.uart._ import midas.models.AXI4BundleWithEdge +import firesim.util.IOMatchingMIDASEnvironment import java.io.File + +object FireSimValName { + implicit val valName = ValName("TestHarness") +} +import FireSimValName._ /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -30,7 +36,7 @@ import java.io.File * determine which driver to build. *******************************************************************************/ -class FireSim(implicit p: Parameters) extends RocketSubsystem +class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -44,7 +50,7 @@ class FireSim(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimModuleImp(this) } -class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) +class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -56,8 +62,9 @@ class FireSimModuleImp[+L <: FireSim](l: L) extends RocketSubsystemModuleImp(l) with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp +class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module) -class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem +class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -70,7 +77,7 @@ class FireSimNoNIC(implicit p: Parameters) extends RocketSubsystem override lazy val module = new FireSimNoNICModuleImp(this) } -class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemModuleImp(l) +class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -82,7 +89,9 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNIC](l: L) extends RocketSubsystemMod with CanHaveRocketMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem +class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module) + +class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -96,7 +105,7 @@ class FireBoom(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomModuleImp(this) } -class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -109,7 +118,9 @@ class FireBoomModuleImp[+L <: FireBoom](l: L) extends BoomRocketSubsystemModuleI with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem +class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module) + +class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM @@ -122,7 +133,7 @@ class FireBoomNoNIC(implicit p: Parameters) extends BoomRocketSubsystem override lazy val module = new FireBoomNoNICModuleImp(this) } -class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsystemModuleImp(l) +class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp @@ -134,6 +145,8 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNIC](l: L) extends BoomRocketSubsys with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp +class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module) + case object NumNodes extends Field[Int] class SupernodeIO( @@ -152,10 +165,10 @@ class SupernodeIO( } -class FireSimSupernode(implicit p: Parameters) extends Module { +class FireSimSupernodeDUT(implicit p: Parameters) extends Module { val nNodes = p(NumNodes) val nodes = Seq.fill(nNodes) { - Module(LazyModule(new FireSim).module) + Module(LazyModule(new FireSimDUT).module) } val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) @@ -178,3 +191,4 @@ class FireSimSupernode(implicit p: Parameters) extends Module { } } } +class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT) From e18e59ccda4fe1f0b053626c45560bbb1d53c066 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 6 Sep 2019 12:48:41 -0700 Subject: [PATCH 03/61] [FireSim] Use black-box instantiations of endpoints --- .../scala/DefaultFireSimEnvironment.scala | 72 +++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 27 +------ .../firechip/src/main/scala/Targets.scala | 26 ++----- 3 files changed, 78 insertions(+), 47 deletions(-) create mode 100644 generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala new file mode 100644 index 00000000..0d22e3fb --- /dev/null +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -0,0 +1,72 @@ +package firesim.firesim + +import chisel3._ +import chisel3.experimental.RawModule + +import freechips.rocketchip.config.Parameters +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + +import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} + +import junctions.{NastiKey, NastiParameters} +import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import firesim.endpoints._ +import firesim.configs.MemModelKey + +// Creates a wrapper module that instantiates endpoints based on the scala type +// of the Target (_not_ its IO). This avoids needing to duplicate environments +// (essentially test harnesses) for each target type, +// +// You could just as well create a custom environment (essentially, test +// harness) module that instantiates endpoints explicitly, or add methods to +// your target traits that instantiate the endpoint there (i.e., akin to +// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match +// on the types rather than change trait code. + +class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { + val clock = IO(Input(Clock())) + val reset = WireInit(false.B) + withClockAndReset(clock, reset) { + val target = Module(LazyModule(dutGen()).module) + val peekPokeEndpoint = PeekPokeEndpoint(reset) + // A Seq of partial functions that will instantiate the right endpoint only + // if that Mixin trait is present in the target's class instance + // + // TODO: If we like this PF approach, register them in the config instead of centralizing them here + val endpointBinders = Seq[PartialFunction[Any, Seq[IsEndpoint]]]( + { case t: HasPeripheryDebugModuleImp => + t.debug.clockeddmi.foreach({ cdmi => + cdmi.dmi.req.valid := false.B + cdmi.dmi.req.bits := DontCare + cdmi.dmi.resp.ready := false.B + cdmi.dmiClock := false.B.asClock + cdmi.dmiReset := false.B + }) + Seq() + }, + { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, + { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, + { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, + { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => + (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (io zip node.in).map({ case (axi4Bundle, (_, edge)) => + val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, + axi4Bundle.ar.bits.addr.getWidth, + axi4Bundle.ar.bits.id.getWidth) + val fasedP = p.alterPartial({ + case NastiKey => nastiKey + case FasedAXI4Edge => Some(edge) + }) + FASEDEndpoint(axi4Bundle, reset, p(MemModelKey)(fasedP))(fasedP) + }) + }).toSeq + }, + { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } + ) + // Apply each partial function to the DUT; collecting the generated endpoints + val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + } +} diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 531c067a..ac2ed1d0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -14,7 +14,6 @@ import testchipip.{BlockDeviceKey, BlockDeviceConfig} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import icenet._ -import firesim.util.{EndpointKey, TieOffDebug} import firesim.endpoints._ import firesim.configs.WithDefaultMemModel @@ -37,33 +36,15 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) => }) class WithUARTKey extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(UARTEndpoint) case PeripheryUARTKey => List(UARTParams( address = BigInt(0x54000000L), nTxEntries = 256, nRxEntries = 256)) }) -class WithSerialEndpoint extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(SerialEndpoint) -}) - -class WithTracerVEndpoint extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(TracerVEndpoint) -}) - -class WithBlockDevice extends Config( - new Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(BlockDevEndpoint, firesim.util.FASEDEndpointMatcher) - }) ++ new testchipip.WithBlockDevice -) - -class WithTieOffDebug extends Config((site, here, up) => { - case EndpointKey => up(EndpointKey) ++ Seq(TieOffDebug) -}) +class WithBlockDevice extends Config(new testchipip.WithBlockDevice) class WithNICKey extends Config((site, here, up) => { - //case EndpointKey => up(EndpointKey) ++ Seq(NICEndpoint) case NICKey => NICConfig( inBufFlits = 8192, ctrlQueueDepth = 64) @@ -122,9 +103,6 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithSerialEndpoint ++ - new WithTracerVEndpoint ++ - new WithTieOffDebug ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -165,9 +143,6 @@ class FireSimBoomConfig extends Config( new WithBoomL2TLBs(1024) ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithSerialEndpoint ++ - new WithTracerVEndpoint ++ - new WithTieOffDebug ++ // Using a small config because it has 64-bit system bus, and compiles quickly new boom.system.SmallBoomConfig) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index e592f5d1..5b905bcc 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -6,6 +6,7 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.diplomacy._ import freechips.rocketchip.tilelink._ import freechips.rocketchip.devices.tilelink._ +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.config.Parameters import freechips.rocketchip.util.{HeterogeneousBag} import freechips.rocketchip.amba.axi4.AXI4Bundle @@ -16,15 +17,14 @@ import icenet._ import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import sifive.blocks.devices.uart._ -import midas.models.AXI4BundleWithEdge -import firesim.util.IOMatchingMIDASEnvironment import java.io.File object FireSimValName { - implicit val valName = ValName("TestHarness") + implicit val valName = ValName("FireSimHarness") } import FireSimValName._ + /******************************************************************************* * Top level DESIGN configurations. These describe the basic instantiations of * the designs being simulated. @@ -40,7 +40,6 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryIceNIC @@ -54,7 +53,6 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryIceNICModuleImpValidOnly @@ -62,13 +60,10 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimDUT).module) - class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryBlockDevice @@ -81,7 +76,6 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp @@ -89,13 +83,12 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystem with CanHaveRocketMultiCycleRegfileImp -class FireSimNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireSimNoNICDUT).module) +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT) class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryIceNIC @@ -109,7 +102,6 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryIceNICModuleImpValidOnly @@ -118,13 +110,10 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomDUT).module) - class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort with HasPeripheryBootROM - with HasNoDebug with HasPeripherySerial with HasPeripheryUART with HasPeripheryBlockDevice @@ -137,7 +126,6 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with HasRTCModuleImp with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp - with HasNoDebugModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp with HasPeripheryBlockDeviceModuleImp @@ -145,14 +133,12 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => LazyModule(new FireBoomNoNICDUT).module) - case object NumNodes extends Field[Int] class SupernodeIO( nNodes: Int, serialWidth: Int, - bagPrototype: HeterogeneousBag[AXI4BundleWithEdge])(implicit p: Parameters) + bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters) extends Bundle { val serial = Vec(nNodes, new SerialIO(serialWidth)) @@ -190,5 +176,3 @@ class FireSimSupernodeDUT(implicit p: Parameters) extends Module { n.debug.clockeddmi.get.dmi.req.bits.op := DontCare } } } - -class FireSimSupernode(implicit p: Parameters) extends IOMatchingMIDASEnvironment(() => new FireSimSupernodeDUT) From 9285155476c8f48eff9d7e64266cda8e70112337 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 6 Sep 2019 14:51:01 -0700 Subject: [PATCH 04/61] [Firechip] Add NIC endpoint; Add environments for all targets --- .../scala/DefaultFireSimEnvironment.scala | 15 ++++-- .../firechip/src/main/scala/Targets.scala | 49 +++---------------- 2 files changed, 18 insertions(+), 46 deletions(-) diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 0d22e3fb..8440a6da 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -3,12 +3,13 @@ package firesim.firesim import chisel3._ import chisel3.experimental.RawModule -import freechips.rocketchip.config.Parameters +import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} +import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} import midas.widgets.{IsEndpoint, PeekPokeEndpoint} @@ -26,11 +27,14 @@ import firesim.configs.MemModelKey // SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match // on the types rather than change trait code. +case object NumNodes extends Field[Int](1) + class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { val clock = IO(Input(Clock())) val reset = WireInit(false.B) withClockAndReset(clock, reset) { - val target = Module(LazyModule(dutGen()).module) + // Instantiate multiple instances of the DUT to implement supernode + val targets = Seq.fill(p(NumNodes))(Module(LazyModule(dutGen()).module)) val peekPokeEndpoint = PeekPokeEndpoint(reset) // A Seq of partial functions that will instantiate the right endpoint only // if that Mixin trait is present in the target's class instance @@ -48,6 +52,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p Seq() }, { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, + { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => @@ -66,7 +71,9 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p }, { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } ) - // Apply each partial function to the DUT; collecting the generated endpoints - val endpoints = endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + // Apply each partial function to each DUT instance + for ((target) <- targets) { + endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) + } } } diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 5b905bcc..5111819f 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -60,6 +60,8 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp( with HasTraceIOImp with CanHaveRocketMultiCycleRegfileImp +class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) + class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort @@ -110,6 +112,8 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModu with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp +class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT) + class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration with CanHaveFASEDOptimizedMasterAXI4MemPort @@ -133,46 +137,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSub with ExcludeInvalidBoomAssertions with CanHaveBoomMultiCycleRegfileImp -case object NumNodes extends Field[Int] +class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT) -class SupernodeIO( - nNodes: Int, - serialWidth: Int, - bagPrototype: HeterogeneousBag[midas.models.AXI4BundleWithEdge])(implicit p: Parameters) - extends Bundle { - - val serial = Vec(nNodes, new SerialIO(serialWidth)) - val mem_axi = Vec(nNodes, bagPrototype.cloneType) - val bdev = Vec(nNodes, new BlockDeviceIO) - val net = Vec(nNodes, new NICIOvonly) - val uart = Vec(nNodes, new UARTPortIO) - - override def cloneType = new SupernodeIO(nNodes, serialWidth, bagPrototype).asInstanceOf[this.type] -} - - -class FireSimSupernodeDUT(implicit p: Parameters) extends Module { - val nNodes = p(NumNodes) - val nodes = Seq.fill(nNodes) { - Module(LazyModule(new FireSimDUT).module) - } - - val io = IO(new SupernodeIO(nNodes, SERIAL_IF_WIDTH, nodes(0).mem_axi4.get)) - - io.mem_axi.zip(nodes.map(_.mem_axi4)).foreach { - case (out, mem_axi4) => out <> mem_axi4.get - } - io.serial <> nodes.map(_.serial) - io.bdev <> nodes.map(_.bdev) - io.net <> nodes.map(_.net) - io.uart <> nodes.map(_.uart(0)) - nodes.foreach{ case n => { - n.debug.clockeddmi.get.dmi.req.valid := false.B - n.debug.clockeddmi.get.dmi.resp.ready := false.B - n.debug.clockeddmi.get.dmiClock := clock - n.debug.clockeddmi.get.dmiReset := reset.toBool - n.debug.clockeddmi.get.dmi.req.bits.data := DontCare - n.debug.clockeddmi.get.dmi.req.bits.addr := DontCare - n.debug.clockeddmi.get.dmi.req.bits.op := DontCare - } } -} +// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1 +class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) From ac8385a0c51843a4ff91bd6812b3983387fabf76 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 13 Sep 2019 00:40:50 -0700 Subject: [PATCH 05/61] [firechip] Remove unneeded FASED target Mixin --- .../scala/DefaultFireSimEnvironment.scala | 3 +- .../src/main/scala/TargetMixins.scala | 54 ------------------- .../firechip/src/main/scala/Targets.scala | 16 +++--- 3 files changed, 10 insertions(+), 63 deletions(-) diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 8440a6da..80750f52 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -6,6 +6,7 @@ import chisel3.experimental.RawModule import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} @@ -55,7 +56,7 @@ class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, - { case t: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp => + { case t: CanHaveMasterAXI4MemPortModuleImp => (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => (io zip node.in).map({ case (axi4Bundle, (_, edge)) => val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 535e354a..bf50db80 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -38,60 +38,6 @@ trait HasDefaultBusConfiguration { } } - -/** Copied from RC and modified to change the IO type of the Imp to include the Diplomatic edges - * associated with each port. This drives FASED functional model sizing - */ -trait CanHaveFASEDOptimizedMasterAXI4MemPort { this: BaseSubsystem => - val module: CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp - - val memAXI4Node = p(ExtMem).map { case MemoryPortParams(memPortParams, nMemoryChannels) => - val portName = "axi4" - val device = new MemoryDevice - - val memAXI4Node = AXI4SlaveNode(Seq.tabulate(nMemoryChannels) { channel => - val base = AddressSet.misaligned(memPortParams.base, memPortParams.size) - val filter = AddressSet(channel * mbus.blockBytes, ~((nMemoryChannels-1) * mbus.blockBytes)) - - AXI4SlavePortParameters( - slaves = Seq(AXI4SlaveParameters( - address = base.flatMap(_.intersect(filter)), - resources = device.reg, - regionType = RegionType.UNCACHED, // cacheable - executable = true, - supportsWrite = TransferSizes(1, mbus.blockBytes), - supportsRead = TransferSizes(1, mbus.blockBytes), - interleavedId = Some(0))), // slave does not interleave read responses - beatBytes = memPortParams.beatBytes) - }) - - memAXI4Node := mbus.toDRAMController(Some(portName)) { - AXI4UserYanker() := AXI4IdIndexer(memPortParams.idBits) := TLToAXI4() - } - - memAXI4Node - } -} - -/** Actually generates the corresponding IO in the concrete Module */ -trait CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp extends LazyModuleImp { - val outer: CanHaveFASEDOptimizedMasterAXI4MemPort - - val mem_axi4 = outer.memAXI4Node.map(x => IO(HeterogeneousBag(AXI4BundleWithEdge.fromNode(x.in)))) - (mem_axi4 zip outer.memAXI4Node) foreach { case (io, node) => - (io zip node.in).foreach { case (io, (bundle, _)) => io <> bundle } - } - - def connectSimAXIMem() { - (mem_axi4 zip outer.memAXI4Node).foreach { case (io, node) => - (io zip node.in).foreach { case (io, (_, edge)) => - val mem = LazyModule(new SimAXIMem(edge, size = p(ExtMem).get.master.size)) - Module(mem.module).io.axi4.head <> io - } - } - } -} - /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV endpoint can match on. */ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 5111819f..853b54a5 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -38,7 +38,7 @@ import FireSimValName._ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -51,7 +51,7 @@ class FireSimDUT(implicit p: Parameters) extends RocketSubsystem class FireSimModuleImp[+L <: FireSimDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -64,7 +64,7 @@ class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => ne class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -76,7 +76,7 @@ class FireSimNoNICDUT(implicit p: Parameters) extends RocketSubsystem class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends RocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -89,7 +89,7 @@ class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -102,7 +102,7 @@ class FireBoomDUT(implicit p: Parameters) extends BoomRocketSubsystem class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp @@ -116,7 +116,7 @@ class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => n class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem with HasDefaultBusConfiguration - with CanHaveFASEDOptimizedMasterAXI4MemPort + with CanHaveMasterAXI4MemPort with HasPeripheryBootROM with HasPeripherySerial with HasPeripheryUART @@ -128,7 +128,7 @@ class FireBoomNoNICDUT(implicit p: Parameters) extends BoomRocketSubsystem class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends BoomRocketSubsystemModuleImp(l) with HasRTCModuleImp - with CanHaveFASEDOptimizedMasterAXI4MemPortModuleImp + with CanHaveMasterAXI4MemPortModuleImp with HasPeripheryBootROMModuleImp with HasPeripherySerialModuleImp with HasPeripheryUARTModuleImp From 4c087b5c3f48a7870860f3226d28be833ea447cf Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 17 Sep 2019 23:50:04 -0700 Subject: [PATCH 06/61] [firechip] Remove some antiquated midas imports --- generators/firechip/src/main/scala/SimConfigs.scala | 2 -- generators/firechip/src/main/scala/TargetMixins.scala | 1 - 2 files changed, 3 deletions(-) diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala index 6f6464dc..06e6aa93 100644 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ b/generators/firechip/src/main/scala/SimConfigs.scala @@ -3,8 +3,6 @@ package firesim.firesim import freechips.rocketchip.config.{Parameters, Config, Field} -import midas.{EndpointKey} -import midas.widgets.{EndpointMap} import midas.models._ import firesim.endpoints._ diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index bf50db80..1b8b5f62 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -12,7 +12,6 @@ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} -import midas.models.AXI4BundleWithEdge import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ From 38588b67efcaefe6e9c23184fd981ab65cdf8ffb Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Sep 2019 15:21:08 -0700 Subject: [PATCH 07/61] Bump FireSim, update reset delay in ScalaTests --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 2 +- sims/firesim | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 44c4bff0..7a07e950 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,7 +109,7 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 51 + val resetLength = 50 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") diff --git a/sims/firesim b/sims/firesim index 92fe0e4d..9eaa0dc8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 92fe0e4def4d9bde0c5c36cd9090ef8c60fd0d45 +Subproject commit 9eaa0dc85081a06ad25b3ed21ebf63942f6c061b From 829f8fd84d073372b9081b54b5b4f05c5b8ee53b Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 19 Sep 2019 15:32:09 -0700 Subject: [PATCH 08/61] [firechip] Remove unneeded HasDefaultBusConfiguration --- .../src/main/scala/TargetMixins.scala | 23 ------------------- 1 file changed, 23 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index b40a91ff..46c5f9f8 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -14,29 +14,6 @@ import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} -/** Ties together Subsystem buses in the same fashion done in the example top of Rocket Chip */ -trait HasDefaultBusConfiguration { - this: BaseSubsystem => - // The sbus masters the cbus; here we convert TL-UH -> TL-UL - sbus.crossToBus(cbus, NoCrossing) - - // The cbus masters the pbus; which might be clocked slower - cbus.crossToBus(pbus, SynchronousCrossing()) - - // The fbus masters the sbus; both are TL-UH or TL-C - FlipRendering { implicit p => - sbus.crossFromBus(fbus, SynchronousCrossing()) - } - - // The sbus masters the mbus; here we convert TL-C -> TL-UH - private val BankedL2Params(nBanks, coherenceManager) = p(BankedL2Key) - private val (in, out, halt) = coherenceManager(this) - if (nBanks != 0) { - sbus.coupleTo("coherence_manager") { in :*= _ } - mbus.coupleFrom("coherence_manager") { _ :=* BankBinder(mbus.blockBytes * (nBanks-1)) :*= out } - } -} - /* Wires out tile trace ports to the top; and wraps them in a Bundle that the * TracerV endpoint can match on. */ From f44f3aacbf522776f417cc0dda74acf935871f94 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Tue, 24 Sep 2019 03:04:27 +0000 Subject: [PATCH 09/61] [FireChip] Allow users to register new EndpointBinders in P --- .../scala/DefaultFireSimEnvironment.scala | 16 ++-- .../src/main/scala/EndpointBinders.scala | 92 +++++++++++++++++++ .../src/main/scala/TargetConfigs.scala | 2 + .../firechip/src/main/scala/Targets.scala | 12 +-- 4 files changed, 110 insertions(+), 12 deletions(-) create mode 100644 generators/firechip/src/main/scala/EndpointBinders.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala index 80750f52..6bb53ed6 100644 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala @@ -1,3 +1,5 @@ +//See LICENSE for license details. + package firesim.firesim import chisel3._ @@ -18,19 +20,21 @@ import midas.models.{FASEDEndpoint, FasedAXI4Edge} import firesim.endpoints._ import firesim.configs.MemModelKey -// Creates a wrapper module that instantiates endpoints based on the scala type -// of the Target (_not_ its IO). This avoids needing to duplicate environments -// (essentially test harnesses) for each target type, +// Creates a wrapper FireSim harness module that instantiates endpoints based +// on the scala type of the Target (_not_ its IO). This avoids needing to +// duplicate harnesses (essentially test harnesses) for each target. // -// You could just as well create a custom environment (essentially, test -// harness) module that instantiates endpoints explicitly, or add methods to +// You could just as well create a custom harness module that instantiates +// endpoints explicitly, or add methods to // your target traits that instantiate the endpoint there (i.e., akin to // SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match // on the types rather than change trait code. +// Determines the number of times to instantiate the DUT in the harness. +// Subsumes legacy supernode support case object NumNodes extends Field[Int](1) -class DefaultFireSimEnvironment[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { +class DefaultFireSimHarness[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { val clock = IO(Input(Clock())) val reset = WireInit(false.B) withClockAndReset(clock, reset) { diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala new file mode 100644 index 00000000..631ad6d9 --- /dev/null +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -0,0 +1,92 @@ +//See LICENSE for license details. + +package firesim.firesim + +import chisel3._ +import chisel3.experimental.RawModule + +import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.diplomacy.{LazyModule} +import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp +import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} +import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp + +import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} +import icenet.HasPeripheryIceNICModuleImpValidOnly + +import junctions.{NastiKey, NastiParameters} +import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import firesim.endpoints._ +import firesim.configs.MemModelKey + + +// A sequence of partial functions that match on the type the DUT (_not_ it's +// IO) to generate an appropriate endpoint. You can add your own endpoint by prepending +// a custom PartialFunction to this Seq +case object EndpointBinders extends Field[Seq[PartialFunction[Any, Seq[IsEndpoint]]]](Seq()) + +// Config sugar that accepts a partial function and prepends it to EndpointBinders +class RegisterEndpointBinder(pf: =>PartialFunction[Any, Seq[IsEndpoint]]) extends Config((site, here, up) => { + case EndpointBinders => pf +: up(EndpointBinders, site) +}) + +// Default FireSim Endpoint binders follow +class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => + target.debug.clockeddmi.foreach({ cdmi => + cdmi.dmi.req.valid := false.B + cdmi.dmi.req.bits := DontCare + cdmi.dmi.resp.ready := false.B + cdmi.dmiClock := false.B.asClock + cdmi.dmiReset := false.B + }) + Seq() +}) + +class WithSerialEndpoint extends RegisterEndpointBinder({ + case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) +}) + +class WithNICEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) +}) + +class WithUARTEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) +}) + +class WithBlockDeviceEndpoint extends RegisterEndpointBinder({ + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) +}) + +class WithFASEDEndpoint extends RegisterEndpointBinder({ + case t: CanHaveMasterAXI4MemPortModuleImp => + implicit val p = t.p + (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => + (io zip node.in).map({ case (axi4Bundle, (_, edge)) => + val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, + axi4Bundle.ar.bits.addr.getWidth, + axi4Bundle.ar.bits.id.getWidth) + val fasedP = p.alterPartial({ + case NastiKey => nastiKey + case FasedAXI4Edge => Some(edge) + }) + FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP) + }) + }).toSeq +}) + +class WithTracerVEndpoint extends RegisterEndpointBinder({ + case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p) +}) + +// Shorthand to register all of the provided endpoints above +class WithDefaultFireSimEndpoints extends Config( + new WithTiedOffDebug ++ + new WithSerialEndpoint ++ + new WithNICEndpoint ++ + new WithUARTEndpoint ++ + new WithBlockDeviceEndpoint ++ + new WithFASEDEndpoint ++ + new WithTracerVEndpoint +) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 91580a29..9906b24e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -107,6 +107,7 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ + new WithDefaultFireSimEndpoints ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -149,6 +150,7 @@ class FireSimBoomConfig extends Config( new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ + new WithDefaultFireSimEndpoints ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 6eac228d..3db3fecc 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -61,7 +61,7 @@ class FireSimModuleImp[+L <: FireSimDUT](l: L) extends SubsystemModuleImp(l) with HasTraceIOImp with CanHaveMultiCycleRegfileImp -class FireSim(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) +class FireSim(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) class FireSimNoNICDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -86,7 +86,7 @@ class FireSimNoNICModuleImp[+L <: FireSimNoNICDUT](l: L) extends SubsystemModule with CanHaveMultiCycleRegfileImp -class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimNoNICDUT) +class FireSimNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimNoNICDUT) class FireBoomDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -113,7 +113,7 @@ class FireBoomModuleImp[+L <: FireBoomDUT](l: L) extends SubsystemModuleImp(l) with ExcludeInvalidBoomAssertions with CanHaveMultiCycleRegfileImp -class FireBoom(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomDUT) +class FireBoom(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomDUT) class FireBoomNoNICDUT(implicit p: Parameters) extends Subsystem with HasHierarchicalBusTopology @@ -138,7 +138,7 @@ class FireBoomNoNICModuleImp[+L <: FireBoomNoNICDUT](l: L) extends SubsystemModu with ExcludeInvalidBoomAssertions with CanHaveMultiCycleRegfileImp -class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireBoomNoNICDUT) +class FireBoomNoNIC(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireBoomNoNICDUT) class FireSimTraceGen(implicit p: Parameters) extends BaseSubsystem with HasHierarchicalBusTopology @@ -151,5 +151,5 @@ class FireSimTraceGenModuleImp(outer: FireSimTraceGen) extends BaseSubsystemModu with HasTraceGenTilesModuleImp with CanHaveMasterAXI4MemPortModuleImp -// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimEnvironment) to something > 1 -class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimEnvironment(() => new FireSimDUT) +// Supernoded-ness comes from setting p(NumNodes) (see DefaultFiresimHarness) to something > 1 +class FireSimSupernode(implicit p: Parameters) extends DefaultFireSimHarness(() => new FireSimDUT) From 4c45d2e48af7ac102f38e17d21750137b7e6d4a3 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 26 Sep 2019 20:49:03 +0000 Subject: [PATCH 10/61] [firechip] Support registration of custom endpoint binders --- .../scala/DefaultFireSimEnvironment.scala | 84 ------------------- .../src/main/scala/EndpointBinders.scala | 18 +--- .../src/main/scala/TargetConfigs.scala | 4 +- .../firechip/src/main/scala/Targets.scala | 1 + sims/firesim | 2 +- 5 files changed, 6 insertions(+), 103 deletions(-) delete mode 100644 generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala diff --git a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala b/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala deleted file mode 100644 index 6bb53ed6..00000000 --- a/generators/firechip/src/main/scala/DefaultFireSimEnvironment.scala +++ /dev/null @@ -1,84 +0,0 @@ -//See LICENSE for license details. - -package firesim.firesim - -import chisel3._ -import chisel3.experimental.RawModule - -import freechips.rocketchip.config.{Field, Parameters} -import freechips.rocketchip.diplomacy.{LazyModule} -import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp -import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} -import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp - -import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp} -import icenet.HasPeripheryIceNICModuleImpValidOnly - -import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint, PeekPokeEndpoint} -import midas.models.{FASEDEndpoint, FasedAXI4Edge} -import firesim.endpoints._ -import firesim.configs.MemModelKey - -// Creates a wrapper FireSim harness module that instantiates endpoints based -// on the scala type of the Target (_not_ its IO). This avoids needing to -// duplicate harnesses (essentially test harnesses) for each target. -// -// You could just as well create a custom harness module that instantiates -// endpoints explicitly, or add methods to -// your target traits that instantiate the endpoint there (i.e., akin to -// SimAXI4Mem). Since cake traits live in Rocket Chip it was easiest to match -// on the types rather than change trait code. - -// Determines the number of times to instantiate the DUT in the harness. -// Subsumes legacy supernode support -case object NumNodes extends Field[Int](1) - -class DefaultFireSimHarness[T <: LazyModule](dutGen: () => T)(implicit val p: Parameters) extends RawModule { - val clock = IO(Input(Clock())) - val reset = WireInit(false.B) - withClockAndReset(clock, reset) { - // Instantiate multiple instances of the DUT to implement supernode - val targets = Seq.fill(p(NumNodes))(Module(LazyModule(dutGen()).module)) - val peekPokeEndpoint = PeekPokeEndpoint(reset) - // A Seq of partial functions that will instantiate the right endpoint only - // if that Mixin trait is present in the target's class instance - // - // TODO: If we like this PF approach, register them in the config instead of centralizing them here - val endpointBinders = Seq[PartialFunction[Any, Seq[IsEndpoint]]]( - { case t: HasPeripheryDebugModuleImp => - t.debug.clockeddmi.foreach({ cdmi => - cdmi.dmi.req.valid := false.B - cdmi.dmi.req.bits := DontCare - cdmi.dmi.resp.ready := false.B - cdmi.dmiClock := false.B.asClock - cdmi.dmiReset := false.B - }) - Seq() - }, - { case t: HasPeripherySerialModuleImp => Seq(SerialEndpoint(t.serial)) }, - { case t: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(t.net)) }, - { case t: HasPeripheryUARTModuleImp => t.uart.map(u => UARTEndpoint(u)) }, - { case t: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(t.bdev, reset)) }, - { case t: CanHaveMasterAXI4MemPortModuleImp => - (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => - (io zip node.in).map({ case (axi4Bundle, (_, edge)) => - val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, - axi4Bundle.ar.bits.addr.getWidth, - axi4Bundle.ar.bits.id.getWidth) - val fasedP = p.alterPartial({ - case NastiKey => nastiKey - case FasedAXI4Edge => Some(edge) - }) - FASEDEndpoint(axi4Bundle, reset, p(MemModelKey)(fasedP))(fasedP) - }) - }).toSeq - }, - { case t: HasTraceIOImp => TracerVEndpoint(t.traceIO) } - ) - // Apply each partial function to each DUT instance - for ((target) <- targets) { - endpointBinders.map(_.lift).flatMap(elaborator => elaborator(target)) - } - } -} diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala index 631ad6d9..0450f8f3 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -3,9 +3,8 @@ package firesim.firesim import chisel3._ -import chisel3.experimental.RawModule -import freechips.rocketchip.config.{Field, Parameters, Config} +import freechips.rocketchip.config.{Field, Config} import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.devices.debug.HasPeripheryDebugModuleImp import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPortModuleImp} @@ -15,23 +14,12 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint, PeekPokeEndpoint} +import midas.widgets.{IsEndpoint} import midas.models.{FASEDEndpoint, FasedAXI4Edge} import firesim.endpoints._ import firesim.configs.MemModelKey +import firesim.util.RegisterEndpointBinder - -// A sequence of partial functions that match on the type the DUT (_not_ it's -// IO) to generate an appropriate endpoint. You can add your own endpoint by prepending -// a custom PartialFunction to this Seq -case object EndpointBinders extends Field[Seq[PartialFunction[Any, Seq[IsEndpoint]]]](Seq()) - -// Config sugar that accepts a partial function and prepends it to EndpointBinders -class RegisterEndpointBinder(pf: =>PartialFunction[Any, Seq[IsEndpoint]]) extends Config((site, here, up) => { - case EndpointBinders => pf +: up(EndpointBinders, site) -}) - -// Default FireSim Endpoint binders follow class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => target.debug.clockeddmi.foreach({ cdmi => cdmi.dmi.req.valid := false.B diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 9906b24e..0e31bb56 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -19,6 +19,7 @@ import tracegen.TraceGenKey import icenet._ import firesim.endpoints._ +import firesim.util.{WithNumNodes} import firesim.configs.WithDefaultMemModel class WithBootROM extends Config((site, here, up) => { @@ -174,9 +175,6 @@ class FireSimBoomQuadCoreConfig extends Config( //********************************************************************************** //* Supernode Configurations //*********************************************************************************/ -class WithNumNodes(n: Int) extends Config((pname, site, here) => { - case NumNodes => n -}) class SupernodeFireSimRocketChipConfig extends Config( new WithNumNodes(4) ++ diff --git a/generators/firechip/src/main/scala/Targets.scala b/generators/firechip/src/main/scala/Targets.scala index 3db3fecc..7ce143dd 100644 --- a/generators/firechip/src/main/scala/Targets.scala +++ b/generators/firechip/src/main/scala/Targets.scala @@ -14,6 +14,7 @@ import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy.LazyModule import utilities.{Subsystem, SubsystemModuleImp} import icenet._ +import firesim.util.DefaultFireSimHarness import testchipip._ import testchipip.SerialAdapter.SERIAL_IF_WIDTH import tracegen.{HasTraceGenTiles, HasTraceGenTilesModuleImp} diff --git a/sims/firesim b/sims/firesim index 9eaa0dc8..bb38ab90 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9eaa0dc85081a06ad25b3ed21ebf63942f6c061b +Subproject commit bb38ab90235847a6f9fafe55f6e1e254a510a890 From 868c2b3b6d1e34ffce40f3f70c01f1207ed13e50 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 26 Sep 2019 20:49:50 +0000 Subject: [PATCH 11/61] [firechip] Make some TracerV tests less strict --- generators/firechip/src/main/scala/TargetMixins.scala | 3 ++- generators/firechip/src/test/scala/ScalaTestSuite.scala | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 46c5f9f8..0c7d2eb9 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -1,6 +1,7 @@ package firesim.firesim import chisel3._ +import chisel3.util.Cat import chisel3.experimental.annotate import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.diplomacy._ @@ -41,7 +42,7 @@ trait HasTraceIOImp extends LazyModuleImp { // Enabled to test TracerV trace capture if (p(PrintTracePort)) { val traceprint = Wire(UInt(512.W)) - traceprint := traceIO.asUInt + traceprint := Cat(traceIO.traces.map(_.asUInt)) printf("TRACEPORT: %x\n", traceprint) } } diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 7a07e950..77415636 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -109,10 +109,10 @@ abstract class FireSimTestSuite( val lines = Source.fromFile(file).getLines.toList lines.filter(_.startsWith("TRACEPORT")).drop(dropLines) } - val resetLength = 50 + val resetLength = 51 val verilatedOutput = getLines(new File(outDir, s"/${verilatedLog}")) val synthPrintOutput = getLines(new File(genDir, s"/TRACEFILE"), resetLength) - assert(verilatedOutput.size == synthPrintOutput.size, "Outputs differ in length") + assert(math.abs(verilatedOutput.size - synthPrintOutput.size) <= 1, "Outputs differ in length") assert(verilatedOutput.nonEmpty) for ( (vPrint, sPrint) <- verilatedOutput.zip(synthPrintOutput) ) { assert(vPrint == sPrint) From c84c5c218e157236e3e4ea5cfca70f77a35e1187 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 27 Sep 2019 20:48:05 +0000 Subject: [PATCH 12/61] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index bb38ab90..4769e5d8 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit bb38ab90235847a6f9fafe55f6e1e254a510a890 +Subproject commit 4769e5d86acf6a9508d2b5a63141dc80a6ef20a6 From 3dbb5508be35e51c20163b8fdd1957a08e885f39 Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Wed, 25 Sep 2019 12:39:17 -0700 Subject: [PATCH 13/61] [docs][ci skip] Information on debug methodology --- docs/Chipyard-Basics/Debugging-RTL.rst | 85 ++++++++++++++++++++++++++ docs/Chipyard-Basics/index.rst | 3 + docs/Simulation/index.rst | 1 + 3 files changed, 89 insertions(+) create mode 100644 docs/Chipyard-Basics/Debugging-RTL.rst diff --git a/docs/Chipyard-Basics/Debugging-RTL.rst b/docs/Chipyard-Basics/Debugging-RTL.rst new file mode 100644 index 00000000..36e101ea --- /dev/null +++ b/docs/Chipyard-Basics/Debugging-RTL.rst @@ -0,0 +1,85 @@ +Debugging RTL +====================== + +While the packaged Chipyard configs and RTL have been tested to work, +users will typically want to build custom chips by adding their own +IP, or by modifying existing Chisel generators. Such changes might introduce +bugs. This section aims to run through a typical debugging flow +using Chipyard. We assume the user has a custom SoC configuration, +and is trying to verify functionality by running some software test. + +Waveforms +--------------------------- + +The default SW simulators do not dump waveforms during execution. To build +simulators with wave dump capabilities use must use the ``debug`` make target. +For example: + +.. code-block:: shell + + make CONFIG=CustomConfig debug + +The ``run-binary-debug`` rule will also automatically build a simulator, +run it on a custom binary, and generate a waveform. For example, to run a +test on ``helloworld.riscv``, use + +.. code-block:: shell + + make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv + +VCS and Verilator also support many additional flags. For example, specifying +the ``+vpdfilesize`` flag in VCS will treat the output file as a circular +buffer, saving disk space for long-running simulations. Refer to the VCS +and Verilator manuals for more information You may use the ``SIM_FLAGS`` +make variable to set additional simulator flags: + +.. code-block:: shell + + make CONFIG=CustomConfig run-binary-debug BINARY=linux.riscv SIM_FLAGS=+vpdfilesize=1024 + +Print Output +--------------------------- + +Both Rocket and BOOM can be configured with varying levels of print output. +For information see the Rocket core source code, or the BOOM `documentation +`__ .website. In addition, developers +may insert arbitrary printfs at arbitrary conditions within the Chisel g +enerators. See the Chisel documentation for information on this. + +Once the cores have been configured with the desired print statements, the +``+verbose`` flag will cause the simulator to print the statements. The following +commands will all generate desired print statements: + +.. code-block:: shell + + make CONFIG=CustomConfig run-binary-debug BINARY=helloworld.riscv + # The below command does the same thing + ./simv-CustomConfig-debug +verbose helloworld.riscv + +Both cores can be configured to print out commit logs, which can then be compared +against a Spike commit log to verify correctness. + +Basic tests +--------------------------- +``riscv-tests`` includes basic ISA-level tests and basic benchmarks. These +are used in Chipyard CI, and should be the first step in verifying a chip's +functionality. The make rule is + +.. code-block:: shell + + make CONFIG=CustomConfig run-asm-tests run-bmark-tests + + +Torture tests +--------------------------- +The RISC-V torture utility generates random RISC-V assembly streams, compiles them, +runs them on both the Spike functional model and the SW simulator, and verifies +identical program behavior. The torture utility can also be configured to run +continuously for stress-testing. The torture utility exists within the ``utilities`` +directory. + +Firesim Debugging +--------------------------- +Chisel printfs, asserts, and waveform generation are also available in FireSim +FPGA-accelerated simulation. See the FireSim docs for more detail. + diff --git a/docs/Chipyard-Basics/index.rst b/docs/Chipyard-Basics/index.rst index 5c97f0ac..4ca236c4 100644 --- a/docs/Chipyard-Basics/index.rst +++ b/docs/Chipyard-Basics/index.rst @@ -18,3 +18,6 @@ Hit next to get started! Chipyard-Components Configs-Parameters-Mixins Initial-Repo-Setup + Debugging-RTL + + diff --git a/docs/Simulation/index.rst b/docs/Simulation/index.rst index fe0fa161..8341c7ae 100644 --- a/docs/Simulation/index.rst +++ b/docs/Simulation/index.rst @@ -20,3 +20,4 @@ Click next to see how to run a simulation. Software-RTL-Simulation FPGA-Accelerated-Simulators + From 48c8e0f571e973115fc52a6bbaeb34e7b59c91fa Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Sat, 28 Sep 2019 18:17:42 -0700 Subject: [PATCH 14/61] [docs][ci skip] Address comments --- .../Debugging-RTL.rst | 12 ++++++++---- docs/Advanced-Concepts/index.rst | 1 + docs/Chipyard-Basics/index.rst | 1 - 3 files changed, 9 insertions(+), 5 deletions(-) rename docs/{Chipyard-Basics => Advanced-Concepts}/Debugging-RTL.rst (87%) diff --git a/docs/Chipyard-Basics/Debugging-RTL.rst b/docs/Advanced-Concepts/Debugging-RTL.rst similarity index 87% rename from docs/Chipyard-Basics/Debugging-RTL.rst rename to docs/Advanced-Concepts/Debugging-RTL.rst index 36e101ea..464c5571 100644 --- a/docs/Chipyard-Basics/Debugging-RTL.rst +++ b/docs/Advanced-Concepts/Debugging-RTL.rst @@ -7,13 +7,16 @@ IP, or by modifying existing Chisel generators. Such changes might introduce bugs. This section aims to run through a typical debugging flow using Chipyard. We assume the user has a custom SoC configuration, and is trying to verify functionality by running some software test. +We also assume the software has already been verified on a functional +simulator, such as Spike or QEMU. This section will focus on debugging +hardware. Waveforms --------------------------- -The default SW simulators do not dump waveforms during execution. To build -simulators with wave dump capabilities use must use the ``debug`` make target. -For example: +The default software RTL simulators do not dump waveforms during execution. +To build simulators with wave dump capabilities use must use the ``debug`` +make target. For example: .. code-block:: shell @@ -81,5 +84,6 @@ directory. Firesim Debugging --------------------------- Chisel printfs, asserts, and waveform generation are also available in FireSim -FPGA-accelerated simulation. See the FireSim docs for more detail. +FPGA-accelerated simulation. See the FireSim +`documentation `__ for more detail. diff --git a/docs/Advanced-Concepts/index.rst b/docs/Advanced-Concepts/index.rst index 2994899c..8194fe1f 100644 --- a/docs/Advanced-Concepts/index.rst +++ b/docs/Advanced-Concepts/index.rst @@ -10,4 +10,5 @@ They expect you to know about Chisel, Parameters, Configs, etc. Top-Testharness Chip-Communication + Debugging-RTL Resources diff --git a/docs/Chipyard-Basics/index.rst b/docs/Chipyard-Basics/index.rst index 4ca236c4..467f147a 100644 --- a/docs/Chipyard-Basics/index.rst +++ b/docs/Chipyard-Basics/index.rst @@ -18,6 +18,5 @@ Hit next to get started! Chipyard-Components Configs-Parameters-Mixins Initial-Repo-Setup - Debugging-RTL From 7a39cbdddcd79d7e2257f6a78f48ca29f9ef7565 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 00:34:29 -0700 Subject: [PATCH 15/61] bump down to innovus 18.1 --- docs/VLSI/Tutorial.rst | 5 +- vlsi/example-vlsi | 4 +- vlsi/example.yml | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 9536 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 668 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 7 files changed, 341 insertions(+), 342 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index 7c2e0d2f..de6e0166 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,8 +54,9 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. + * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). Initial Setup ------------- @@ -83,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index a17f4f0c..264d0d8d 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -36,9 +36,7 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -if {{ [catch {{ exec python3 {script_file} }} msg] }} {{ - puts "$::errorInfo" -}} +exec python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/example.yml b/vlsi/example.yml index d8ca594b..3f8c0f23 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -124,7 +124,7 @@ synthesis.genus.version: "1813" vlsi.core.par_tool: "innovus" vlsi.core.par_tool_path: ["hammer-cadence-plugins/par"] vlsi.core.par_tool_path_meta: "append" -par.innovus.version: "191" +par.innovus.version: "181" par.innovus.design_flow_effort: "standard" par.inputs.gds_merge: true # Calibre options diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 9990b41cb9422c5e429e78f59005ab44cd04acc0..556f117ced6baa701af624cb5670c1bafdc0e7fe 100644 GIT binary patch literal 8556 zcmbuDUuc$99LLZ5I-i*>XZa@wCK&WjL+77T!D7}FN>FK%qRFP)TUoQov=j_Ffk6g_ z6&PgTpdy2c?5fLMb=`HBb=OsNSvP%u@7c#4ACG5e+YcT;_I-a}KJVF{$6j7nxn}dQ zTis}O{^{;sG{ncT1Yp?(@e_ogQuVKfm8CU$F4mU6;1){q@_wcl7_VapKyM zgKqW0OuLHP9gCc+?rXZoUA3g?oO^QV0{y9J_%@vVXZM7=MRKv@e&=rQ|2NNm zb^73k_`5^^4fIivhzc7G3#fK9wblpBY(HaHA{W)Lvk_eXOA8vPxd4K zGI?!Q=(6)eaxv>?j~*mX_9Oo)lWTf>@I!Jj>t~N1Bv1Au|7v+{*66bHLvk_eXOA8v zPxd4KT9a!Y_Q4Oy#jKw_dXPNXkNl6wYx9^cJ3k~BvwrsILGolj@~<KO`5ke)i}=@?<~q_sMJXoGv>*Bp0)O_UJ+KWIyunHo0bx z4}M54X8r8ZgXGD6xazt7~F{XY01xtR5{M-P%G`;q@8 zd2J5rvhzc7G3#fK9wblpBmW_jYYzM1hvZ_`&mKKUp6o~dqw?Au(`Dy}_`3~d2NpS;DPh7W#7F5cOXK7X@E50WSQ(fLowYcr86{p`_$Ie@|YU_jTF% zA-S0Kvquk-C;O5AqRBNM_~3`+V%Eaz1gaxv>?j~*mX_9OpwlWQh?@I!Jj>t~N1Bv1Au|5x(be51?G56Q)>pFMhz zJlT)@H%zYi&Idmv7qfo$=t1&iKk|Psug#CT?EH{i%=+1*2g#HD$bZx1nxB2}Lvk_e zXOA8vPxgbq@z+rM`@c39=&%3keZYoyynZ)7ug|8xIsX3fiPNs}`=oP5doSw`Op{!U z{h>eg`Df1ksh|IbpMu|L{@yFoH2>7=clFPqzpQ=!j`01d-ETIc{T%E)KyqX3Up~+N zntAra_s4U8|KayH_x{d#zW+V*>>rqC|HxeXUAMl!U)j_>Q9amj3tg9ei{JU1bIm@t zxThL9dG__zc(`Bk`_-gd+Ea~>of|yU8XY`wwD(v^>)yWGTbqhn-8I+dqSo@7YfDjU zRn4`vsP$0I^;A)7ZO!#`QR~r~YgNhQ~%)gX68&-X1-Ec5K}KXH)XreA<`j7M}BJ z%3FBWYbkHxd9SCuh5x>Mo$?m`8*?M&)k9M9bN(Ua)uU3( zBtA%*ipF9uA_Y<}{Xq#?WFJI&SbPXE0x1v?kqyL`r23wFe&4&7+w{Xd^U#Hz&z&W&G^Hb>CR|@J zrAaf*ck$fjB-+EdXm8*fY~cYs^x}B(piPmJ$Ti;#;9&SEcUT)6iFVaLjAN}&9R%C`#8_arfJCnP_i-@#e?UG+bQ6%sHNUvX`6-t;zeu88 z_1B3{ZV;bDuKDq8=ck-Tj%;*-cVKl;u2DQ`JHBGIn;--}QFC_af?^$&?pekwkRT=ln#PY#JsB3J!x z@yQ@i%*utCy{G@c-{FaZ#X|B(XRSmi%)(lK8alQH;PYg5uZe^`b)(pmx)gz z*ZksN&L_iAe4))%|El=pHRl&eFKyZ;Sg-0S+{i8V8`sB$(H!+D^^|y;p*2E`~ ztNtqS$%^L`ze*YrO&-VN&Id79_SI>V)e3J7v ziCp!!icb#VIkt#IuKL|L*j_)`ljtTQk*j_zK3Nu@M6UViynWr(N$2ewu8wV2eaz4H z`a_cQHi=yI4~S15l=G6vRiE=d$$6hduKG*m{3Pdn61nDc-X|Y!{-5r@#jEc8DX+QL zuh0J(|E&1rIq^y4>h$W^~fd~%`qBy!C!+;x7+ zd(JPAXjlD9;**!fCy}fE3GvA>@k!*Wzf*j2SbP$>>i3FI_K8m-SN(SJ$@$`w$TdIx z-SDQXW9~RVC34ljARaj`K8alQ4~tJ86Q4w``UB#VJH#iEXMMMRmhtbD9Q#Fvy`#q1 zoW$sTPEj;u4ch(Pz&I{&b2rtRWhQ7Q0 z|J(O@{X@z6e|rA1x4$&mW|7eTFTw3Q+Q;Pnm9eJA{~uass(@6*p!KOO`1nK{#cihC8Skl8tHb^5(GUBIa23{%&Q?r&XFO8>xPMQz)<3X$`AhG4Tn#FjPb&8H z41KV7M|EVzcf?+c`L1H-;f~aYs{JF?_dlv_+gl&myv+A{?lh{l+_PHYsYcbheXDJ1 zRP6=dYDXGXd(pSruGeha8tP9nbkEswba}%o@&j?vHx%m3&8#sF1JZJA#B)@|Ao?knpp7C7%(b^rT(;PbF*r M_3LG=TmnP$4-bSh761SM diff --git a/vlsi/extra_libraries/example/ExampleDCO.lef b/vlsi/extra_libraries/example/ExampleDCO.lef index ad850e2c..7a0594b7 100644 --- a/vlsi/extra_libraries/example/ExampleDCO.lef +++ b/vlsi/extra_libraries/example/ExampleDCO.lef @@ -6,374 +6,374 @@ MACRO ExampleDCO CLASS BLOCK ; ORIGIN 0 0 ; FOREIGN ExampleDCO 0 0 ; - SIZE 128.0 BY 128.0 ; + SIZE 129.536 BY 125.536 ; SYMMETRY X Y ; PIN VDD DIRECTION INOUT ; USE POWER ; - PORT - LAYER M7 ; - RECT 32.96 124.0 33.6 128.0 ; - END + PORT + LAYER M5 ; + RECT 10.608 121.536 11.088 125.536 ; + END END VDD PIN VSS DIRECTION INOUT ; USE GROUND ; - PORT + PORT LAYER M5 ; - RECT 93.12 124.0 93.76 128.0 ; - END + RECT 11.712 121.536 12.192 125.536 ; + END END VSS - PIN col_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 113.28 4.0 113.664 ; - END - END col_sel_b[13] - PIN col_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 107.648 4.0 108.032 ; - END - END col_sel_b[11] - PIN col_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 90.752 4.0 91.136 ; - END - END col_sel_b[5] - PIN col_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 110.464 4.0 110.848 ; - END - END col_sel_b[12] - PIN col_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 104.832 4.0 105.216 ; - END - END col_sel_b[10] - PIN col_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 102.016 4.0 102.4 ; - END - END col_sel_b[9] - PIN col_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 99.2 4.0 99.584 ; - END - END col_sel_b[8] - PIN col_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 96.384 4.0 96.768 ; - END - END col_sel_b[7] - PIN col_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 93.568 4.0 93.952 ; - END - END col_sel_b[6] - PIN col_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 87.936 4.0 88.32 ; - END - END col_sel_b[4] - PIN col_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 85.12 4.0 85.504 ; - END - END col_sel_b[3] - PIN col_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 82.304 4.0 82.688 ; - END - END col_sel_b[2] - PIN col_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 79.488 4.0 79.872 ; - END - END col_sel_b[1] - PIN col_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 76.672 4.0 77.056 ; - END - END col_sel_b[0] - PIN row_sel_b[14] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 71.04 4.0 71.424 ; - END - END row_sel_b[14] - PIN row_sel_b[13] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 68.224 4.0 68.608 ; - END - END row_sel_b[13] - PIN row_sel_b[12] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 65.408 4.0 65.792 ; - END - END row_sel_b[12] - PIN row_sel_b[11] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 62.592 4.0 62.976 ; - END - END row_sel_b[11] - PIN row_sel_b[10] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 59.776 4.0 60.16 ; - END - END row_sel_b[10] - PIN row_sel_b[9] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 56.96 4.0 57.344 ; - END - END row_sel_b[9] - PIN row_sel_b[8] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 54.144 4.0 54.528 ; - END - END row_sel_b[8] - PIN row_sel_b[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 51.328 4.0 51.712 ; - END - END row_sel_b[7] - PIN row_sel_b[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 48.512 4.0 48.896 ; - END - END row_sel_b[6] - PIN row_sel_b[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 45.696 4.0 46.08 ; - END - END row_sel_b[5] - PIN row_sel_b[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 42.88 4.0 43.264 ; - END - END row_sel_b[4] - PIN row_sel_b[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 40.064 4.0 40.448 ; - END - END row_sel_b[3] - PIN row_sel_b[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 37.248 4.0 37.632 ; - END - END row_sel_b[2] - PIN row_sel_b[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 34.432 4.0 34.816 ; - END - END row_sel_b[1] - PIN row_sel_b[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 31.616 4.0 32.0 ; - END - END row_sel_b[0] - PIN code_regulator[7] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 28.8 4.0 29.184 ; - END - END code_regulator[7] - PIN code_regulator[6] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 25.984 4.0 26.368 ; - END - END code_regulator[6] - PIN code_regulator[5] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 23.168 4.0 23.552 ; - END - END code_regulator[5] - PIN code_regulator[4] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 20.352 4.0 20.736 ; - END - END code_regulator[4] - PIN code_regulator[3] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 17.536 4.0 17.92 ; - END - END code_regulator[3] - PIN code_regulator[2] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 14.72 4.0 15.104 ; - END - END code_regulator[2] - PIN code_regulator[1] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 11.904 4.0 12.288 ; - END - END code_regulator[1] - PIN code_regulator[0] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 9.088 4.0 9.472 ; - END - END code_regulator[0] - PIN row_sel_b[15] - DIRECTION INPUT ; - USE SIGNAL ; - PORT - LAYER M4 ; - RECT 0.0 73.856 4.0 74.24 ; - END - END row_sel_b[15] PIN dither DIRECTION INPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 0.0 6.272 4.0 6.656 ; - END + RECT 0.0 0.384 4.0 0.768 ; + END END dither + PIN row_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 1.536 4.0 1.92 ; + END + END row_sel_b[0] + PIN row_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 2.688 4.0 3.072 ; + END + END row_sel_b[1] + PIN row_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 3.84 4.0 4.224 ; + END + END row_sel_b[2] + PIN row_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 4.992 4.0 5.376 ; + END + END row_sel_b[3] + PIN row_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 6.144 4.0 6.528 ; + END + END row_sel_b[4] + PIN row_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 7.296 4.0 7.68 ; + END + END row_sel_b[5] + PIN row_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 8.448 4.0 8.832 ; + END + END row_sel_b[6] + PIN row_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 9.6 4.0 9.984 ; + END + END row_sel_b[7] + PIN row_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 10.752 4.0 11.136 ; + END + END row_sel_b[8] + PIN row_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 11.904 4.0 12.288 ; + END + END row_sel_b[9] + PIN row_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 13.056 4.0 13.44 ; + END + END row_sel_b[10] + PIN row_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 14.208 4.0 14.592 ; + END + END row_sel_b[11] + PIN row_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 15.36 4.0 15.744 ; + END + END row_sel_b[12] + PIN row_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 16.512 4.0 16.896 ; + END + END row_sel_b[13] + PIN row_sel_b[14] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 17.664 4.0 18.048 ; + END + END row_sel_b[14] + PIN row_sel_b[15] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 18.816 4.0 19.2 ; + END + END row_sel_b[15] + PIN col_sel_b[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 19.968 4.0 20.352 ; + END + END col_sel_b[0] + PIN col_sel_b[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 21.12 4.0 21.504 ; + END + END col_sel_b[1] + PIN col_sel_b[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 22.272 4.0 22.656 ; + END + END col_sel_b[2] + PIN col_sel_b[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 23.424 4.0 23.808 ; + END + END col_sel_b[3] + PIN col_sel_b[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 24.576 4.0 24.96 ; + END + END col_sel_b[4] + PIN col_sel_b[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 25.728 4.0 26.112 ; + END + END col_sel_b[5] + PIN col_sel_b[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 26.88 4.0 27.264 ; + END + END col_sel_b[6] + PIN col_sel_b[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 28.032 4.0 28.416 ; + END + END col_sel_b[7] + PIN col_sel_b[8] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 29.184 4.0 29.568 ; + END + END col_sel_b[8] + PIN col_sel_b[9] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 30.336 4.0 30.72 ; + END + END col_sel_b[9] + PIN col_sel_b[10] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 31.488 4.0 31.872 ; + END + END col_sel_b[10] + PIN col_sel_b[11] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 32.64 4.0 33.024 ; + END + END col_sel_b[11] + PIN col_sel_b[12] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 33.792 4.0 34.176 ; + END + END col_sel_b[12] + PIN col_sel_b[13] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 34.944 4.0 35.328 ; + END + END col_sel_b[13] + PIN code_regulator[0] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 36.096 4.0 36.48 ; + END + END code_regulator[0] + PIN code_regulator[1] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 37.248 4.0 37.632 ; + END + END code_regulator[1] + PIN code_regulator[2] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 38.4 4.0 38.784 ; + END + END code_regulator[2] + PIN code_regulator[3] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 39.552 4.0 39.936 ; + END + END code_regulator[3] + PIN code_regulator[4] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 40.704 4.0 41.088 ; + END + END code_regulator[4] + PIN code_regulator[5] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 41.856 4.0 42.24 ; + END + END code_regulator[5] + PIN code_regulator[6] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 43.008 4.0 43.392 ; + END + END code_regulator[6] + PIN code_regulator[7] + DIRECTION INPUT ; + USE SIGNAL ; + PORT + LAYER M4 ; + RECT 0.0 44.16 4.0 44.544 ; + END + END code_regulator[7] PIN sleep_b DIRECTION INPUT ; USE SIGNAL ; - PORT - LAYER M5 ; - RECT 9.792 0.0 10.176 4.0 ; - END + PORT + LAYER M4 ; + RECT 0.0 45.312 4.0 45.696 ; + END END sleep_b PIN clock DIRECTION OUTPUT ; USE SIGNAL ; - PORT + PORT LAYER M4 ; - RECT 124.0 70.864 128.0 71.248 ; - END + RECT 125.536 0.384 129.536 0.768 ; + END END clock - OBS + OBS LAYER M1 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M2 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M3 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M4 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M5 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M6 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M7 ; - RECT 4.0 4.0 124.0 124.0 ; + RECT 4.0 0.0 125.536 121.536 ; LAYER M8 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER M9 ; - RECT 0.0 0.0 128.0 128.0 ; + RECT 0.0 0.0 129.536 121.536 ; LAYER Pad ; - RECT 0.0 0.0 128.0 128.0 ; - END + RECT 0.0 0.0 129.536 121.536 ; + END END ExampleDCO END LIBRARY diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..88226815 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd diff --git a/vlsi/hammer-cadence-plugins b/vlsi/hammer-cadence-plugins index 06ce365b..5e93f2e7 160000 --- a/vlsi/hammer-cadence-plugins +++ b/vlsi/hammer-cadence-plugins @@ -1 +1 @@ -Subproject commit 06ce365b36e4b8520372968a5ef2a301afe8d5d6 +Subproject commit 5e93f2e72f5af06aaca0fbfa53e8d043d92e2341 From b0b3e016e5c682ba06772c0978739130b8bb5e3d Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 23 Sep 2019 16:59:27 -0700 Subject: [PATCH 16/61] scripts: Remove unnecessary experimental-blocks ignore Polluting the global .gitconfig is not appreciated in any case. --- scripts/init-submodules-no-riscv-tools.sh | 2 -- 1 file changed, 2 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 627c9285..cf3244c4 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -13,7 +13,6 @@ scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" # in the submodule tree will get pulled anyway git config submodule.toolchains/riscv-tools.update none git config submodule.toolchains/esp-tools.update none -git config --global submodule.experimental-blocks.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none # Disable updates to the hammer tool plugins repos @@ -24,7 +23,6 @@ git submodule update --init --recursive #--jobs 8 # unignore riscv-tools,catapult-shell2 globally git config --unset submodule.toolchains/riscv-tools.update git config --unset submodule.toolchains/esp-tools.update -git config --global --unset submodule.experimental-blocks.update git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update From 2f1e5e994b5c867fac6a7c90fb1dc72dd4082b2d Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Mon, 23 Sep 2019 23:47:39 -0700 Subject: [PATCH 17/61] toolchains: Flatten riscv-tools submodule This allows individual components to be better maintained following the deprecation of riscv-tools. Eliminate non-essential submodules. build-static-libfesvr.sh is no longer necessary since libfesvr.a is built as part of the riscv-isa-sim build. For simplicity, only riscv-gnu-toolchain is now pre-built instead of the entirety of riscv-tools. --- .gitmodules | 22 ++- scripts/build-static-libfesvr.sh | 21 --- scripts/build-toolchains.sh | 151 ++++++------------ scripts/build-util.sh | 89 +++++++++++ scripts/init-submodules-no-riscv-tools.sh | 28 ++-- toolchains/esp-tools | 1 - toolchains/riscv-tools | 1 - toolchains/riscv-tools/riscv-gnu-toolchain | 1 + .../riscv-tools/riscv-gnu-toolchain-prebuilt | 1 + toolchains/riscv-tools/riscv-isa-sim | 1 + toolchains/riscv-tools/riscv-pk | 1 + toolchains/riscv-tools/riscv-tests | 1 + 12 files changed, 174 insertions(+), 144 deletions(-) delete mode 100755 scripts/build-static-libfesvr.sh create mode 100644 scripts/build-util.sh delete mode 160000 toolchains/esp-tools delete mode 160000 toolchains/riscv-tools create mode 160000 toolchains/riscv-tools/riscv-gnu-toolchain create mode 160000 toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt create mode 160000 toolchains/riscv-tools/riscv-isa-sim create mode 160000 toolchains/riscv-tools/riscv-pk create mode 160000 toolchains/riscv-tools/riscv-tests diff --git a/.gitmodules b/.gitmodules index 35addf76..d7691ffb 100644 --- a/.gitmodules +++ b/.gitmodules @@ -34,12 +34,22 @@ [submodule "generators/block-inclusivecache-sifive"] path = generators/sifive-cache url = https://github.com/sifive/block-inclusivecache-sifive.git -[submodule "toolchains/riscv-tools"] - path = toolchains/riscv-tools - url = https://github.com/freechipsproject/rocket-tools.git -[submodule "toolchains/esp-tools"] - path = toolchains/esp-tools - url = https://github.com/ucb-bar/esp-tools.git +[submodule "toolchains/riscv-tools/riscv-gnu-toolchain"] + path = toolchains/riscv-tools/riscv-gnu-toolchain + url = https://github.com/riscv/riscv-gnu-toolchain.git +[submodule "toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt"] + path = toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt + url = https://github.com/ucb-bar/chipyard-toolchain-prebuilt.git + shallow = true +[submodule "toolchains/riscv-tools/riscv-isa-sim"] + path = toolchains/riscv-tools/riscv-isa-sim + url = https://github.com/riscv/riscv-isa-sim.git +[submodule "toolchains/riscv-tools/riscv-pk"] + path = toolchains/riscv-tools/riscv-pk + url = https://github.com/riscv/riscv-pk.git +[submodule "toolchains/riscv-tools/riscv-tests"] + path = toolchains/riscv-tools/riscv-tests + url = https://github.com/riscv/riscv-tests.git [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git diff --git a/scripts/build-static-libfesvr.sh b/scripts/build-static-libfesvr.sh deleted file mode 100755 index d5b7f896..00000000 --- a/scripts/build-static-libfesvr.sh +++ /dev/null @@ -1,21 +0,0 @@ -#!/usr/bin/env bash - -# This ungodly script surreptitiously builds an archive from existing fesvr objects -# Invoke from riscv-fesvr/build - -if [ "x$RISCV" = "x" ] -then - echo "Please set the RISCV environment variable to your preferred install path." - exit 1 -fi - -set -e - -objs=$(make -n -f <( - echo 'include Makefile' - echo '$(info $(value fesvr_objs))' - ) | head -n 1) - -ar rcs -o libfesvr.a $objs -cp -f libfesvr.a "${RISCV}/lib" - diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 76680f79..734398c3 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -6,11 +6,8 @@ set -e set -o pipefail -unamestr=$(uname) RDIR=$(pwd) -: ${CHIPYARD_DIR:=$(pwd)} #default value is the PWD unless overridden - -PRECOMPILED_REPO_HASH=56a40961c98db5e8f904f15dc6efd0870bfefd9e +CHIPYARD_DIR="${CHIPYARD_DIR:-$(git rev-parse --show-toplevel)}" usage() { echo "usage: ${0} [riscv-tools | esp-tools | ec2fast]" @@ -23,18 +20,13 @@ usage() { error() { echo "${0##*/}: ${1}" >&2 } - -#taken from riscv-tools to check for open-ocd autoconf versions -check_version() { - "$1" --version | awk "NR==1 {if (\$NF>$2) {exit 0} exit 1}" || { - error "${3} requires at least ${1} version ${2}" - exit 1 - } +die() { + error "$1" + exit "${2:--1}" } TOOLCHAIN="riscv-tools" EC2FASTINSTALL="false" -FASTINSTALL="false" while getopts 'hH-:' opt ; do case $opt in @@ -64,33 +56,6 @@ elif [ -n "$1" ] ; then TOOLCHAIN="$1" fi - -if [ "$EC2FASTINSTALL" = "true" ]; then - if [ "$TOOLCHAIN" = "riscv-tools" ]; then - cd "$RDIR" - git clone https://github.com/firesim/firesim-riscv-tools-prebuilt.git - cd firesim-riscv-tools-prebuilt - git checkout "$PRECOMPILED_REPO_HASH" - PREBUILTHASH="$(cat HASH)" - git -C "${CHIPYARD_DIR}" submodule update --init "toolchains/${TOOLCHAIN}" - cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" - GITHASH="$(git rev-parse HEAD)" - cd "$RDIR" - echo "prebuilt hash: $PREBUILTHASH" - echo "git hash: $GITHASH" - if [[ $PREBUILTHASH == $GITHASH && "$EC2FASTINSTALL" == "true" ]]; then - FASTINSTALL=true - echo "Using fast pre-compiled install for riscv-tools" - else - error 'error: hash of precompiled toolchain does not match the riscv-tools submodule hash' - exit -1 - fi - else - error "error: unsupported precompiled toolchain: ${TOOLCHAIN}" - exit -1 - fi -fi - INSTALL_DIR="$TOOLCHAIN-install" RISCV="$(pwd)/$INSTALL_DIR" @@ -98,52 +63,57 @@ RISCV="$(pwd)/$INSTALL_DIR" # install risc-v tools export RISCV="$RISCV" -if [ "$FASTINSTALL" = true ]; then - cd firesim-riscv-tools-prebuilt - ./installrelease.sh - mv distrib "$RISCV" - # copy HASH in case user wants it later - cp HASH "$RISCV" - cd "$RDIR" - rm -rf firesim-riscv-tools-prebuilt +cd "${CHIPYARD_DIR}" + +SRCDIR="$(pwd)/toolchains/${TOOLCHAIN}" +[ -d "${SRCDIR}" ] || die "unsupported toolchain: ${TOOLCHAIN}" +. ./scripts/build-util.sh + + +if [ "${EC2FASTINSTALL}" = true ] ; then + [ "${TOOLCHAIN}" = 'riscv-tools' ] || + die "unsupported precompiled toolchain: ${TOOLCHAIN}" + + echo '=> Fetching pre-built toolchain' + module=toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt + git config --unset submodule."${module}".update || : + git submodule update --init --depth 1 "${module}" + + echo '==> Verifying toolchain version hash' + # Find commit hash without initializing the submodule + hashsrc="$(git ls-tree -d HEAD "${SRCDIR}/riscv-gnu-toolchain" | { + unset IFS && read -r _ type obj _ && + test -n "${obj}" && test "${type}" = 'commit' && echo "${obj}" + }; )" || + die 'failed to obtain riscv-gnu-toolchain submodule hash' "$?" + + read -r hashbin < "${module}/HASH" || + die 'failed to obtain riscv-gnu-toolchain-prebuilt hash' "$?" + + echo "==> ${hashsrc}" + [ "${hashsrc}" = "${hashbin}" ] || + die "pre-built version mismatch: ${hashbin}" + + echo '==> Installing pre-built toolchain' + "${MAKE}" -C "${module}" DESTDIR="${RISCV}" install + git submodule deinit "${module}" || : + else - mkdir -p "$RISCV" - git -C "${CHIPYARD_DIR}" submodule update --init --recursive "toolchains/${TOOLCHAIN}" #--jobs 8 - cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" - - # Scale number of parallel make jobs by hardware thread count - ncpu="$(getconf _NPROCESSORS_ONLN || # GNU - getconf NPROCESSORS_ONLN || # *BSD, Solaris - nproc --all || # Linux - sysctl -n hw.ncpu || # *BSD, OS X - :)" 2>/dev/null - case ${ncpu} in - ''|*[^0-9]*) ;; # Ignore non-integer values - *) export MAKEFLAGS="-j ${ncpu}" ;; - esac - - #build the actual toolchain - #./build.sh - source build.common - echo "Starting RISC-V Toolchain build process" - build_project riscv-fesvr --prefix="${RISCV}" - build_project riscv-isa-sim --prefix="${RISCV}" --with-fesvr="${RISCV}" - build_project riscv-gnu-toolchain --prefix="${RISCV}" - CC= CXX= build_project riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf - build_project riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" - echo -e "\\nRISC-V Toolchain installation completed!" - - # build static libfesvr library for linking into firesim driver (or others) - cd riscv-fesvr/build - "${CHIPYARD_DIR}/scripts/build-static-libfesvr.sh" - cd "$RDIR" - # build linux toolchain - cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN/riscv-gnu-toolchain/build" - make linux - echo -e "\\nRISC-V Linux GNU Toolchain installation completed!" - + module_prepare riscv-gnu-toolchain qemu + module_build riscv-gnu-toolchain --prefix="${RISCV}" + echo '==> Building GNU/Linux toolchain' + module_make riscv-gnu-toolchain linux fi +module_all riscv-isa-sim --prefix="${RISCV}" +# build static libfesvr library for linking into firesim driver (or others) +echo '==> Installing libfesvr static library' +module_make riscv-isa-sim libfesvr.a +cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/" + +CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf +module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" + cd "$RDIR" { @@ -153,20 +123,3 @@ cd "$RDIR" echo "export LD_LIBRARY_PATH=\${RISCV}/lib\${LD_LIBRARY_PATH:+":\${LD_LIBRARY_PATH}"}" } > env.sh echo "Toolchain Build Complete!" - -if [ "$FASTINSTALL" = "false" ]; then - # commands that can't run on EC2 (specifically, OpenOCD because of autoconf version_ - # see if the instance info page exists. if not, we are not on ec2. - # this is one of the few methods that works without sudo - if wget -T 1 -t 3 -O /dev/null http://169.254.169.254/; then - echo "Skipping RISC-V OpenOCD" - else - echo "Building RISC-V OpenOCD" - cd "$CHIPYARD_DIR/toolchains/$TOOLCHAIN" - check_version automake 1.14 "OpenOCD build" - check_version autoconf 2.64 "OpenOCD build" - build_project riscv-openocd --prefix="${RISCV}" --enable-remote-bitbang --enable-jtag_vpi --disable-werror - echo -e "\\nRISC-V OpenOCD installation completed!" - cd "$RDIR" - fi -fi diff --git a/scripts/build-util.sh b/scripts/build-util.sh new file mode 100644 index 00000000..5ca38147 --- /dev/null +++ b/scripts/build-util.sh @@ -0,0 +1,89 @@ +# Derived from +# https://github.com/riscv/riscv-tools/blob/master/build.common + +[ -n "${SRCDIR}" ] || exit 1 + +# Scale number of parallel make jobs by hardware thread count +ncpu="${NPROC:-$(getconf _NPROCESSORS_ONLN || # GNU + getconf NPROCESSORS_ONLN || # *BSD, Solaris + nproc --all || # Linux + sysctl -n hw.ncpu || # *BSD, OS X + :)}" 2>/dev/null +case ${ncpu} in +''|*[!0-9]*) ;; # Ignore non-integer values +*) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; +esac + +MAKE=$(command -v gmake || command -v make) +readonly MAKE + + +module_prepare() ( # [ignored-submodule..] + set -e + name=$1 + shift + + dir="${SRCDIR}/${name}" + echo "=> Starting ${name} build" + echo "==> Initializing ${name} submodule" + if [ $# -gt 0 ] ; then + git submodule update --init "${dir}" + while [ -n "$1" ] ; do + git -C "${dir}" config submodule."${1}".update none + shift + done + fi + git submodule update --init --recursive "${dir}" +) + +module_run() ( # + set -e + cd "${SRCDIR}/${1}" + shift + "$@" +) + +module_make() ( # + set -e -o pipefail + cd "${SRCDIR}/${1}/build" + shift + "${MAKE}" "$@" | tee "build-${1:-make}.log" +) + +module_build() ( # [configure-arg..] + set -e -o pipefail + name=$1 + shift + + cd "${SRCDIR}/${name}" + + if [ -e build ] ; then + echo "==> Removing existing ${name}/build directory" + rm -rf build + fi + if ! [ -e configure ] ; then + echo "==> Updating autoconf files for ${name}" + find . -iname configure.ac -type f -print0 | + while read -r -d '' file ; do + mkdir -p -- "${file%/*}/m4" + done + autoreconf -i + fi + + mkdir -p build + cd build + { + export PATH="${RISCV:+${RISCV}/bin:}${PATH}" + echo "==> Configuring ${name}" + ../configure "$@" + echo "==> Building ${name}" + "${MAKE}" + echo "==> Installing ${name}" + "${MAKE}" install + } 2>&1 | tee build.log +) + +module_all() { # [configure-arg..] + module_prepare "$1" + module_build "$@" +} diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index cf3244c4..e17b67ef 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -4,15 +4,13 @@ set -e set -o pipefail -unamestr=$(uname) -RDIR=$(pwd) -scripts_dir="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )" +RDIR=$(git rev-parse --show-toplevel) -# ignore riscv-tools for submodule init recursive -# you must do this globally (otherwise riscv-tools deep -# in the submodule tree will get pulled anyway -git config submodule.toolchains/riscv-tools.update none -git config submodule.toolchains/esp-tools.update none +# Ignore toolchain submodules +cd "$RDIR" +for name in toolchains/*/*/ ; do + git config submodule."${name%/}".update none +done # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none # Disable updates to the hammer tool plugins repos @@ -20,9 +18,10 @@ git config submodule.vlsi/hammer-cadence-plugins.update none git config submodule.vlsi/hammer-synopsys-plugins.update none git config submodule.vlsi/hammer-mentor-plugins.update none git submodule update --init --recursive #--jobs 8 -# unignore riscv-tools,catapult-shell2 globally -git config --unset submodule.toolchains/riscv-tools.update -git config --unset submodule.toolchains/esp-tools.update +# Un-ignore toolchain submodules +for name in toolchains/*/*/ ; do + git config --unset submodule."${name%/}".update +done git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update @@ -30,9 +29,6 @@ git config --unset submodule.vlsi/hammer-mentor-plugins.update # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update -cd "${scripts_dir}/../sims" -git submodule update --init firesim -cd firesim/sim -git submodule update --init midas -cd "$RDIR" +git submodule update --init sims/firesim +git -C sims/firesim submodule update --init sim/midas git config submodule.sims/firesim.update none diff --git a/toolchains/esp-tools b/toolchains/esp-tools deleted file mode 160000 index dcb6012f..00000000 --- a/toolchains/esp-tools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit dcb6012f77101e793948cc90ac31b3735a9f3f6d diff --git a/toolchains/riscv-tools b/toolchains/riscv-tools deleted file mode 160000 index bce7b5e3..00000000 --- a/toolchains/riscv-tools +++ /dev/null @@ -1 +0,0 @@ -Subproject commit bce7b5e363957c134f944769e677354467b7e4ed diff --git a/toolchains/riscv-tools/riscv-gnu-toolchain b/toolchains/riscv-tools/riscv-gnu-toolchain new file mode 160000 index 00000000..2855d823 --- /dev/null +++ b/toolchains/riscv-tools/riscv-gnu-toolchain @@ -0,0 +1 @@ +Subproject commit 2855d823a6e93d50af604264b02ced951e80de67 diff --git a/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt b/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt new file mode 160000 index 00000000..5e32a015 --- /dev/null +++ b/toolchains/riscv-tools/riscv-gnu-toolchain-prebuilt @@ -0,0 +1 @@ +Subproject commit 5e32a0157f91ebfb5c7ea7113fce28bf40016fa4 diff --git a/toolchains/riscv-tools/riscv-isa-sim b/toolchains/riscv-tools/riscv-isa-sim new file mode 160000 index 00000000..9443c1db --- /dev/null +++ b/toolchains/riscv-tools/riscv-isa-sim @@ -0,0 +1 @@ +Subproject commit 9443c1dbac0301faf3a47c5e6914cc7dcb34983e diff --git a/toolchains/riscv-tools/riscv-pk b/toolchains/riscv-tools/riscv-pk new file mode 160000 index 00000000..a3e4ac61 --- /dev/null +++ b/toolchains/riscv-tools/riscv-pk @@ -0,0 +1 @@ +Subproject commit a3e4ac61d2b1ff37a22b9193b85d3b94273e80cb diff --git a/toolchains/riscv-tools/riscv-tests b/toolchains/riscv-tools/riscv-tests new file mode 160000 index 00000000..249796ce --- /dev/null +++ b/toolchains/riscv-tools/riscv-tests @@ -0,0 +1 @@ +Subproject commit 249796cec94d75ff10ca034153e206a319e87158 From b4ed5eb61bf6615716fb06b3a49ab879971436c4 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Tue, 24 Sep 2019 03:58:19 -0700 Subject: [PATCH 18/61] toolchains: Optionally build riscv-openocd with a separate script --- .gitmodules | 3 +++ scripts/build-openocd.sh | 24 ++++++++++++++++++++++++ toolchains/riscv-tools/riscv-openocd | 1 + 3 files changed, 28 insertions(+) create mode 100755 scripts/build-openocd.sh create mode 160000 toolchains/riscv-tools/riscv-openocd diff --git a/.gitmodules b/.gitmodules index d7691ffb..284318c6 100644 --- a/.gitmodules +++ b/.gitmodules @@ -50,6 +50,9 @@ [submodule "toolchains/riscv-tools/riscv-tests"] path = toolchains/riscv-tools/riscv-tests url = https://github.com/riscv/riscv-tests.git +[submodule "toolchains/riscv-tools/riscv-openocd"] + path = toolchains/riscv-tools/riscv-openocd + url = https://github.com/riscv/riscv-openocd.git [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git diff --git a/scripts/build-openocd.sh b/scripts/build-openocd.sh new file mode 100755 index 00000000..0075fdbe --- /dev/null +++ b/scripts/build-openocd.sh @@ -0,0 +1,24 @@ +#!/usr/bin/env bash + +# exit script if any command fails +set -e +set -o pipefail + +RDIR=$(git rev-parse --show-toplevel) + +if [ -z "${RISCV}" ] ; then + ! [ -r "${RDIR}/env.sh" ] || . "${RDIR}/env.sh" + if [ -z "${RISCV}" ] ; then + echo "${0}: set the RISCV environment variable to desired install path" + exit 1 + fi +fi + +SRCDIR="${RDIR}/toolchains/riscv-tools" +. "${RDIR}/scripts/build-util.sh" + +git config --unset submodule.toolchains/riscv-tools/riscv-openocd.update || : +module_prepare riscv-openocd +module_run riscv-openocd ./bootstrap +module_build riscv-openocd --prefix="${RISCV}" \ + --enable-remote-bitbang --enable-jtag_vpi --disable-werror diff --git a/toolchains/riscv-tools/riscv-openocd b/toolchains/riscv-tools/riscv-openocd new file mode 160000 index 00000000..7c82a7b9 --- /dev/null +++ b/toolchains/riscv-tools/riscv-openocd @@ -0,0 +1 @@ +Subproject commit 7c82a7b9d5b7d8b71e0a66826705ec141db718c3 From 361a9bf1d89b8174326a464dce23002d9df17870 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 25 Sep 2019 21:26:55 -0700 Subject: [PATCH 19/61] toolchains: Flatten esp-tools submodule --- .gitignore | 1 + .gitmodules | 12 ++++++++++++ toolchains/esp-tools/riscv-gnu-toolchain | 1 + toolchains/esp-tools/riscv-isa-sim | 1 + toolchains/esp-tools/riscv-pk | 1 + toolchains/esp-tools/riscv-tests | 1 + 6 files changed, 17 insertions(+) create mode 160000 toolchains/esp-tools/riscv-gnu-toolchain create mode 160000 toolchains/esp-tools/riscv-isa-sim create mode 160000 toolchains/esp-tools/riscv-pk create mode 160000 toolchains/esp-tools/riscv-tests diff --git a/.gitignore b/.gitignore index fe0f53ff..7c1463a4 100644 --- a/.gitignore +++ b/.gitignore @@ -12,5 +12,6 @@ target .DS_Store env.sh riscv-tools-install +esp-tools-install tags *~ diff --git a/.gitmodules b/.gitmodules index 284318c6..4c23765e 100644 --- a/.gitmodules +++ b/.gitmodules @@ -53,6 +53,18 @@ [submodule "toolchains/riscv-tools/riscv-openocd"] path = toolchains/riscv-tools/riscv-openocd url = https://github.com/riscv/riscv-openocd.git +[submodule "toolchains/esp-tools/riscv-gnu-toolchain"] + path = toolchains/esp-tools/riscv-gnu-toolchain + url = https://github.com/ucb-bar/esp-gnu-toolchain.git +[submodule "toolchains/esp-tools/riscv-isa-sim"] + path = toolchains/esp-tools/riscv-isa-sim + url = https://github.com/ucb-bar/esp-isa-sim.git +[submodule "toolchains/esp-tools/riscv-pk"] + path = toolchains/esp-tools/riscv-pk + url = https://github.com/riscv/riscv-pk.git +[submodule "toolchains/esp-tools/riscv-tests"] + path = toolchains/esp-tools/riscv-tests + url = https://github.com/ucb-bar/esp-tests.git [submodule "vlsi/hammer"] path = vlsi/hammer url = https://github.com/ucb-bar/hammer.git diff --git a/toolchains/esp-tools/riscv-gnu-toolchain b/toolchains/esp-tools/riscv-gnu-toolchain new file mode 160000 index 00000000..9f532293 --- /dev/null +++ b/toolchains/esp-tools/riscv-gnu-toolchain @@ -0,0 +1 @@ +Subproject commit 9f532293985d08b0c176d96c7b650e5f433780e1 diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim new file mode 160000 index 00000000..92f2f467 --- /dev/null +++ b/toolchains/esp-tools/riscv-isa-sim @@ -0,0 +1 @@ +Subproject commit 92f2f467c00caa991379ba55ece7118f068c2218 diff --git a/toolchains/esp-tools/riscv-pk b/toolchains/esp-tools/riscv-pk new file mode 160000 index 00000000..a3e4ac61 --- /dev/null +++ b/toolchains/esp-tools/riscv-pk @@ -0,0 +1 @@ +Subproject commit a3e4ac61d2b1ff37a22b9193b85d3b94273e80cb diff --git a/toolchains/esp-tools/riscv-tests b/toolchains/esp-tools/riscv-tests new file mode 160000 index 00000000..f1370d05 --- /dev/null +++ b/toolchains/esp-tools/riscv-tests @@ -0,0 +1 @@ +Subproject commit f1370d054389fc83974fc820985b5c51693b8f9d From 383b58542fabddce8193b72f919d5785a637bfed Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 25 Sep 2019 22:20:20 -0700 Subject: [PATCH 20/61] vcs: Statically link against libfesvr libfesvr.so is no longer built after fesvr merged with riscv-isa-sim. --- sims/vcs/Makefile | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/sims/vcs/Makefile b/sims/vcs/Makefile index 6a65d0a2..aeda8a1b 100644 --- a/sims/vcs/Makefile +++ b/sims/vcs/Makefile @@ -48,8 +48,7 @@ VCS_CC_OPTS = \ -CC "-I$(VCS_HOME)/include" \ -CC "-I$(RISCV)/include" \ -CC "-std=c++11" \ - -CC "-Wl,-rpath,$(RISCV)/lib" \ - $(RISCV)/lib/libfesvr.so + $(RISCV)/lib/libfesvr.a VCS_NONCC_OPTS = \ +lint=all,noVCDE,noONGS,noUI \ From dbd7e49c094e67e5081e8ca7b99ea6af88aa796d Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 26 Sep 2019 13:43:30 -0700 Subject: [PATCH 21/61] ci: Bump docker image to 0.0.11 Building glibc now requires Python 3.4+. --- .circleci/config.yml | 46 ++++++++++++++++++++++---------------------- 1 file changed, 23 insertions(+), 23 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 88ec3e45..855d7aba 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -7,7 +7,7 @@ version: 2 jobs: commit-on-master-check: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -19,7 +19,7 @@ jobs: .circleci/check-commit.sh install-riscv-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -43,7 +43,7 @@ jobs: - "/home/riscvuser/riscv-tools-install" install-esp-toolchain: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -67,7 +67,7 @@ jobs: - "/home/riscvuser/esp-tools-install" install-verilator: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -90,7 +90,7 @@ jobs: - "/home/riscvuser/verilator" build-extra-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -116,7 +116,7 @@ jobs: - "/home/riscvuser/project/tests" prepare-example: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -145,7 +145,7 @@ jobs: - "/home/riscvuser/project" prepare-boomrocketexample: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -174,7 +174,7 @@ jobs: - "/home/riscvuser/project" prepare-boom: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -203,7 +203,7 @@ jobs: - "/home/riscvuser/project" prepare-rocketchip: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -232,7 +232,7 @@ jobs: - "/home/riscvuser/project" prepare-blockdevrocketchip: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -261,7 +261,7 @@ jobs: - "/home/riscvuser/project" prepare-hwacha: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -290,7 +290,7 @@ jobs: - "/home/riscvuser/project" prepare-firesim: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -319,7 +319,7 @@ jobs: - "/home/riscvuser/project" prepare-fireboom: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -348,7 +348,7 @@ jobs: - "/home/riscvuser/project" prepare-firesim-clockdiv: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -377,7 +377,7 @@ jobs: - "/home/riscvuser/project" midasexamples-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -398,7 +398,7 @@ jobs: command: .circleci/run-midasexamples-tests.sh example-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -422,7 +422,7 @@ jobs: command: .circleci/run-tests.sh example boomrocketexample-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -446,7 +446,7 @@ jobs: command: .circleci/run-tests.sh boomrocketexample boom-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -470,7 +470,7 @@ jobs: command: .circleci/run-tests.sh boom rocketchip-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -494,7 +494,7 @@ jobs: command: .circleci/run-tests.sh rocketchip hwacha-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -518,7 +518,7 @@ jobs: command: .circleci/run-tests.sh hwacha firesim-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -545,7 +545,7 @@ jobs: command: .circleci/run-firesim-tests.sh firesim fireboom-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb @@ -573,7 +573,7 @@ jobs: no_output_timeout: 20m firesim-clockdiv-run-tests: docker: - - image: riscvboom/riscvboom-images:0.0.10 + - image: riscvboom/riscvboom-images:0.0.11 environment: JVM_OPTS: -Xmx3200m # Customize the JVM maximum heap limit TERM: dumb From 090f3c68c32dfae5eee00743b9565d896d123207 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 26 Sep 2019 19:11:23 -0700 Subject: [PATCH 22/61] ci: Limit toolchain builds to two concurrent jobs This helps avoid OOM conditions with CircleCI instances. --- .circleci/build-toolchains.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/build-toolchains.sh b/.circleci/build-toolchains.sh index 63f47505..b43d2eda 100755 --- a/.circleci/build-toolchains.sh +++ b/.circleci/build-toolchains.sh @@ -14,5 +14,5 @@ if [ ! -d "$HOME/$1-install" ]; then cd $HOME # init all submodules including the tools - CHIPYARD_DIR=$LOCAL_CHIPYARD_DIR $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 + CHIPYARD_DIR="$LOCAL_CHIPYARD_DIR" NPROC=2 $LOCAL_CHIPYARD_DIR/scripts/build-toolchains.sh $1 fi From a6b8301f0fa14eea50ad4979fb768c2bf11e8e80 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 26 Sep 2019 23:04:34 -0700 Subject: [PATCH 23/61] ci: Increment toolchain cache keys to clear cache Generate hashfiles from normalized output of git-submodule status. (Interestingly, the old method also worked after submodule flattening.) --- .circleci/config.yml | 46 ++++++++++++++++++++-------------------- .circleci/create-hash.sh | 13 ++++++------ 2 files changed, 30 insertions(+), 29 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 855d7aba..d0453176 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -31,14 +31,14 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - run: name: Building riscv-tools toolchain command: | .circleci/build-toolchains.sh riscv-tools no_output_timeout: 120m - save_cache: - key: riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + key: riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} paths: - "/home/riscvuser/riscv-tools-install" install-esp-toolchain: @@ -55,14 +55,14 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + - esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} - run: name: Building esp-tools toolchain command: | .circleci/build-toolchains.sh esp-tools no_output_timeout: 120m - save_cache: - key: esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + key: esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} paths: - "/home/riscvuser/esp-tools-install" install-verilator: @@ -105,7 +105,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - run: name: Build extra tests command: .circleci/build-extra-tests.sh @@ -131,7 +131,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -160,7 +160,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -189,7 +189,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -218,7 +218,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -247,7 +247,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -276,7 +276,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + - esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -305,7 +305,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -334,7 +334,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -363,7 +363,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -389,7 +389,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - verilator-installed-v3-{{ checksum "sims/verilator/verilator.mk" }} @@ -410,7 +410,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - example-{{ .Branch }}-{{ .Revision }} @@ -434,7 +434,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - boomrocketexample-{{ .Branch }}-{{ .Revision }} @@ -458,7 +458,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - boom-{{ .Branch }}-{{ .Revision }} @@ -482,7 +482,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - rocketchip-{{ .Branch }}-{{ .Revision }} @@ -506,7 +506,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - esp-tools-installed-v1-{{ checksum "../esp-tools.hash" }} + - esp-tools-installed-v2-{{ checksum "../esp-tools.hash" }} - restore_cache: keys: - hwacha-{{ .Branch }}-{{ .Revision }} @@ -530,7 +530,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - firesim-{{ .Branch }}-{{ .Revision }} @@ -557,7 +557,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - fireboom-{{ .Branch }}-{{ .Revision }} @@ -585,7 +585,7 @@ jobs: .circleci/create-hash.sh - restore_cache: keys: - - riscv-tools-installed-v1-{{ checksum "../riscv-tools.hash" }} + - riscv-tools-installed-v2-{{ checksum "../riscv-tools.hash" }} - restore_cache: keys: - firesim-clockdiv-{{ .Branch }}-{{ .Revision }} diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh index 84a75244..63dfa242 100755 --- a/.circleci/create-hash.sh +++ b/.circleci/create-hash.sh @@ -4,6 +4,7 @@ # turn echo on and error on earliest command set -ex +set -o pipefail # get shared variables SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" @@ -12,10 +13,10 @@ source $SCRIPT_DIR/defaults.sh # enter bhd repo cd $LOCAL_CHIPYARD_DIR -# get the version of riscv-tools from the git submodule hash -git submodule status | grep "riscv-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/riscv-tools.hash -git submodule status | grep "esp-tools" | awk '{print$1}' | grep -o "[[:alnum:]]*" >> $HOME/esp-tools.hash - +# Use normalized output of git-submodule status as hashfile +for tools in 'riscv-tools' 'esp-tools' ; do + git submodule status "toolchains/${tools}" | while read -r line ; do + echo "${line#[!0-9a-f]}" + done > "${HOME}/${tools}.hash" +done echo "Hashfile for riscv-tools and esp-tools created in $HOME" -echo "Contents: riscv-tools:$(cat $HOME/riscv-tools.hash)" -echo "Contents: esp-tools:$(cat $HOME/esp-tools.hash)" From c7b252aa09773364781a03bbf498782573ee8585 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 27 Sep 2019 22:18:56 +0000 Subject: [PATCH 24/61] toolchains: Check for GNU make 4.x GNU make 4.x is needed to cross-compile glibc 2.28 and newer. This ensures the problem is caught earlier on CentOS release 7.6, whose default make version remains 3.82. --- scripts/build-toolchains.sh | 7 +++++++ scripts/build-util.sh | 2 +- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 734398c3..738b5ae7 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -99,6 +99,13 @@ if [ "${EC2FASTINSTALL}" = true ] ; then git submodule deinit "${module}" || : else + "${MAKE}" --version | ( + read -r makever + case ${makever} in + 'GNU Make '[4-9]\.*|'GNU Make '[1-9][0-9]) ;; + *) false ;; + esac; ) || die 'obsolete make version; need GNU make 4.x or later' + module_prepare riscv-gnu-toolchain qemu module_build riscv-gnu-toolchain --prefix="${RISCV}" echo '==> Building GNU/Linux toolchain' diff --git a/scripts/build-util.sh b/scripts/build-util.sh index 5ca38147..be58a6a1 100644 --- a/scripts/build-util.sh +++ b/scripts/build-util.sh @@ -14,7 +14,7 @@ case ${ncpu} in *) export MAKEFLAGS="-j ${ncpu} ${MAKEFLAGS}" ;; esac -MAKE=$(command -v gmake || command -v make) +MAKE=$(command -v gnumake || command -v gmake || command -v make) readonly MAKE From 1e40014b8e0a7d7ff63ca67f01975e7b784b9988 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Wed, 2 Oct 2019 13:10:17 -0700 Subject: [PATCH 25/61] firesim: Bump for firemarshal update --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4769e5d8..26ffba7c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4769e5d86acf6a9508d2b5a63141dc80a6ef20a6 +Subproject commit 26ffba7cbca2982fef6b221a7abbc51d5cdc4b62 From bb19f67aba60b2c5a99855708adca32a83397241 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 18:50:34 -0700 Subject: [PATCH 26/61] fix innovus 18.1 not executing python script --- vlsi/example-vlsi | 7 ++++++- vlsi/hammer | 2 +- 2 files changed, 7 insertions(+), 2 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 264d0d8d..516ef588 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,6 +24,8 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here +set_db route_design_bottom_routing_layer 2 +set_db route_design_top_routing_layer 7 ''') return True @@ -36,7 +38,10 @@ def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: set fp [open "{script_file}" "w"] puts -nonewline $fp "{script_text}" close $fp -exec python3 {script_file} + +# Innovus <19.1 appends some bad LD_LIBRARY_PATHS, so remove them before executing python +set env(LD_LIBRARY_PATH) [join [lsearch -not -all -inline [split $env(LD_LIBRARY_PATH) ":"] "*INNOVUS*"] ":"] +python3 {script_file} '''.format(script_text=x.technology.scale_gds_script(x.output_gds_filename), script_file=os.path.join(x.run_dir, "gds_scale.py"))) return True diff --git a/vlsi/hammer b/vlsi/hammer index 88226815..d8fad54d 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 88226815243ae922ccd0d9d3810e3b6fcb6c97fd +Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 From dd79c54c965b926f6a44fcb7789ad3372ac7493f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Wed, 2 Oct 2019 19:04:57 -0700 Subject: [PATCH 27/61] bump hammer --- vlsi/hammer | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/vlsi/hammer b/vlsi/hammer index d8fad54d..b5024772 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit d8fad54d125548e50bd65dffa3a53f001e412300 +Subproject commit b50247729bc536522ae42e8adb5e38277095775b From f7d09957e907f50bfa2b4e4ac7422bd35f871f87 Mon Sep 17 00:00:00 2001 From: Abraham Gonzalez Date: Thu, 3 Oct 2019 10:34:23 -0700 Subject: [PATCH 28/61] Add warning directive for Mac/Windows warnings --- docs/Quick-Start.rst | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/docs/Quick-Start.rst b/docs/Quick-Start.rst index 542e3a30..ee7518c4 100644 --- a/docs/Quick-Start.rst +++ b/docs/Quick-Start.rst @@ -5,8 +5,10 @@ Requirements ------------------------------------------- Chipyard is developed and tested on Linux-based systems. -It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. -Working under Windows is not recommended. + +.. Warning:: It is possible to use this on macOS or other BSD-based systems, although GNU tools will need to be installed; it is also recommended to install the RISC-V toolchain from ``brew``. + +.. Warning:: Working under Windows is not recommended. Setting up the Chipyard Repo ------------------------------------------- From 4bf982ad09a699f5d8be2f44795de216147ddbb3 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 3 Oct 2019 20:30:03 +0000 Subject: [PATCH 29/61] sha3: Bump RTL for tutorial enhancements --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index 83dd1955..b364cd36 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit 83dd1955a9a6f277addfbcc65394986e73fc03b2 +Subproject commit b364cd367ceb8636b8dbec3c46bf1aab1788b2c3 From 2dc8c7c143eeab3a02c9dc4a39ec48055aade020 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Thu, 3 Oct 2019 20:40:12 +0000 Subject: [PATCH 30/61] sha3: Update submodule URL The original URL should still redirect. --- .gitmodules | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/.gitmodules b/.gitmodules index 4c23765e..180a68bc 100644 --- a/.gitmodules +++ b/.gitmodules @@ -77,9 +77,9 @@ [submodule "tools/treadle"] path = tools/treadle url = https://github.com/freechipsproject/treadle.git -[submodule "generators/rocc-template"] +[submodule "generators/sha3"] path = generators/sha3 - url = https://github.com/ucb-bar/rocc-template.git + url = https://github.com/ucb-bar/sha3.git [submodule "tools/firrtl-interpreter"] path = tools/firrtl-interpreter url = https://github.com/freechipsproject/firrtl-interpreter.git From 41c560e5a8c20c831765fdc358c535880b4b078b Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 18:47:04 -0400 Subject: [PATCH 31/61] Add symlink to firemarshal to software/firemarshal. Marshal still lives in firesim for now, but can be accessed from chipyard top. --- scripts/init-submodules-no-riscv-tools.sh | 27 ++++++++++++++++++----- sims/firesim | 2 +- software/firemarshal | 1 + 3 files changed, 23 insertions(+), 7 deletions(-) create mode 120000 software/firemarshal diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index e17b67ef..667f33b4 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -6,6 +6,18 @@ set -o pipefail RDIR=$(git rev-parse --show-toplevel) +NO_FIRESIM=false + +while test $# -gt 0 +do + case "$1" in + --no-firesim) + NO_FIRESIM=true; + ;; + esac + shift +done + # Ignore toolchain submodules cd "$RDIR" for name in toolchains/*/*/ ; do @@ -26,9 +38,12 @@ git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update -# Renable firesim and init only the required submodules to provide -# all required scala deps, without doing a full build-setup -git config --unset submodule.sims/firesim.update -git submodule update --init sims/firesim -git -C sims/firesim submodule update --init sim/midas -git config submodule.sims/firesim.update none +if [ "NO_FIRESIM" = false ]; then + # Renable firesim and init only the required submodules to provide + # all required scala deps, without doing a full build-setup + git config --unset submodule.sims/firesim.update + git submodule update --init sims/firesim + git -C sims/firesim submodule update --init sim/midas + git -C sims/firesim submodule update --init --recursive sw/firesim-software + git config submodule.sims/firesim.update none +fi diff --git a/sims/firesim b/sims/firesim index 26ffba7c..ffe68ac7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 26ffba7cbca2982fef6b221a7abbc51d5cdc4b62 +Subproject commit ffe68ac7f69795b2cccf7d9510facd5e2db4edc6 diff --git a/software/firemarshal b/software/firemarshal new file mode 120000 index 00000000..c1e20e80 --- /dev/null +++ b/software/firemarshal @@ -0,0 +1 @@ +../sims/firesim/sw/firesim-software/ \ No newline at end of file From dcddf2c842679dfdc819fbcb7371f84a0b9b16d2 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 20:20:41 -0400 Subject: [PATCH 32/61] Fix typo in firesim initialization in init-submodules-no-riscv-tools.sh --- scripts/init-submodules-no-riscv-tools.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 667f33b4..da34adf0 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -38,7 +38,7 @@ git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update -if [ "NO_FIRESIM" = false ]; then +if [ $NO_FIRESIM = false ]; then # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update From e5713a4127d26e0a514b00e5731eb4b1badb9134 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Thu, 3 Oct 2019 20:36:37 -0400 Subject: [PATCH 33/61] Update docs to include path to FireMarshal --- docs/Software/FireMarshal.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/Software/FireMarshal.rst b/docs/Software/FireMarshal.rst index ecc23736..da529f13 100644 --- a/docs/Software/FireMarshal.rst +++ b/docs/Software/FireMarshal.rst @@ -1,5 +1,6 @@ FireMarshal ================= +``software/firemarshal`` FireMarshal is a workload generation tool for RISC-V based systems. It currently only supports the FireSim FPGA-accelerated simulation platform. From d1e3cc558bb21be8beb4a883a7ffcad00de9e157 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 4 Oct 2019 01:09:53 +0000 Subject: [PATCH 34/61] firechip: Add FireSimRocketChipSha3L2Config --- build.sbt | 2 +- generators/firechip/src/main/scala/TargetConfigs.scala | 7 +++++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/build.sbt b/build.sbt index 05a80bba..4d747829 100644 --- a/build.sbt +++ b/build.sbt @@ -188,7 +188,7 @@ lazy val midas = ProjectRef(firesimDir, "midas") lazy val firesimLib = ProjectRef(firesimDir, "firesimLib") lazy val firechip = (project in file("generators/firechip")) - .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") + .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, sha3, utilities, tracegen, midasTargetUtils, midas, firesimLib % "test->test;compile->compile") .settings( commonSettings, testGrouping in Test := isolateAllTests( (definedTests in Test).value ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 0e31bb56..d88ffa25 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -138,6 +138,13 @@ class FireSimRocketChipOctaCoreConfig extends Config( new WithNDuplicatedRocketCores(8) ++ new FireSimRocketChipSingleCoreConfig) +// SHA-3 accelerator config +class FireSimRocketChipSha3L2Config extends Config( + new WithInclusiveCache ++ + new sha3.WithSha3Accel ++ + new WithNBigCores(1) ++ + new FireSimRocketChipConfig) + class FireSimBoomConfig extends Config( new WithBootROM ++ new WithPeripheryBusFrequency(BigInt(3200000000L)) ++ From fcd48ad262532b2b782b72e33a4836f00f43a73f Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 19:36:00 -0700 Subject: [PATCH 35/61] fix power straps --- .gitmodules | 6 +++--- vlsi/example-vlsi | 14 ++++++++++---- vlsi/example.yml | 4 ++++ vlsi/hammer | 2 +- 4 files changed, 18 insertions(+), 8 deletions(-) diff --git a/.gitmodules b/.gitmodules index 35addf76..901df05f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -60,10 +60,10 @@ url = https://github.com/freechipsproject/firrtl-interpreter.git [submodule "vlsi/hammer-cadence-plugins"] path = vlsi/hammer-cadence-plugins - url = git@github.com:ucb-bar/hammer-cadence-plugins.git + url = https://github.com/ucb-bar/hammer-cadence-plugins.git [submodule "vlsi/hammer-synopsys-plugins"] path = vlsi/hammer-synopsys-plugins - url = git@github.com:ucb-bar/hammer-synopsys-plugins.git + url = https://github.com/ucb-bar/hammer-synopsys-plugins.git [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins - url = git@github.com:ucb-bar/hammer-mentor-plugins.git + url = https://github.com/ucb-bar/hammer-mentor-plugins.git diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 516ef588..21ff9598 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 2 +set_db route_design_bottom_routing_layer 1 set_db route_design_top_routing_layer 7 ''') return True @@ -32,6 +32,7 @@ set_db route_design_top_routing_layer 7 def scale_final_gds(x: hammer_vlsi.HammerTool) -> bool: """ Scale the final GDS by a factor of 4 + hammer/src/hammer-vlsi/technology/asap7/__init__.py implements scale_gds_script """ x.append(''' # Write script out to a temporary file and execute it @@ -53,16 +54,21 @@ class ExampleDriver(CLIDriver): # Default set of steps can be found in the CAD tool plugin's __init__.py # make_pre_insertion_hook will execute the custom hook before the specified step - hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # SYNTAX: make_pre_insertion_hook("EXISTING_STEP", INSERTED_HOOK) + # hammer_vlsi.HammerTool.make_pre_insertion_hook("route_design", example_add_fillers), + # make_post_insertion_hook will execute the custom hook after the specified step hammer_vlsi.HammerTool.make_post_insertion_hook("init_design", example_tool_settings), + # make_replacement_hook will replace the specified step with a custom hook - hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # hammer_vlsi.HammerTool.make_replacement_hook("place_tap_cells", example_place_tap_cells), + # make_removal_hook will remove the specified step from the flow hammer_vlsi.HammerTool.make_removal_hook("place_bumps"), + # The target step in any of the above calls may be a default step or another one of your custom hooks - # This is an example of a technology-supplied hook (look in hammer/src/hammer-vlsi/technology/asap7/__init__.py) + # This is an example of a technology-supplied hook hammer_vlsi.HammerTool.make_post_insertion_hook("write_design", scale_final_gds) ] return extra_hooks diff --git a/vlsi/example.yml b/vlsi/example.yml index 3f8c0f23..32dc23d3 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -34,7 +34,11 @@ par.generate_power_straps_options: - M7 - M8 - M9 + pin_layers: + - M9 track_width: 5 + track_width_M2: 7 # minimum allowed + track_width_M3: 7 # minimum allowed track_spacing: 0 track_start: 10 power_utilization: 0.05 diff --git a/vlsi/hammer b/vlsi/hammer index b5024772..e30da8cc 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit b50247729bc536522ae42e8adb5e38277095775b +Subproject commit e30da8cc55297db0d6fe28cfe3309f77450944c0 From ff9f54525d0c9887433130840b0f12cd371896e0 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Thu, 3 Oct 2019 21:35:05 -0700 Subject: [PATCH 36/61] turns out you need to place a 1 core site tall obstruction or else V1's will short from power straps --- vlsi/example.yml | 13 +++++++++---- 1 file changed, 9 insertions(+), 4 deletions(-) diff --git a/vlsi/example.yml b/vlsi/example.yml index 32dc23d3..024e844f 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -36,9 +36,7 @@ par.generate_power_straps_options: - M9 pin_layers: - M9 - track_width: 5 - track_width_M2: 7 # minimum allowed - track_width_M3: 7 # minimum allowed + track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 track_start: 10 power_utilization: 0.05 @@ -58,7 +56,7 @@ vlsi.inputs.placement_constraints: left: 0 right: 0 top: 0 - bottom: 1.08 #must be at least this number + bottom: 0 - path: "Sha3AccelwBB/dco" type: hardmacro x: 108 @@ -67,6 +65,13 @@ vlsi.inputs.placement_constraints: height: 128 orientation: r0 top_layer: M9 + - path: "Sha3AccelwBB/place_obs_bottom" + type: obstruction + obs_types: ["place"] + x: 0 + y: 0 + width: 300 + height: 1.08 # 1 core site tall, necessary to avoid shorts # Pin placement constraints vlsi.inputs.pin_mode: generated From 9fa76f61417d757e35dc85f6470e957ad1f01e2c Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Fri, 4 Oct 2019 00:27:44 -0700 Subject: [PATCH 37/61] post-par sim, align dco straps --- vlsi/example-vlsi | 2 +- vlsi/extra_libraries/example/ExampleDCO.gds | Bin 8556 -> 8556 bytes vlsi/extra_libraries/example/ExampleDCO.lef | 108 ++++++++++---------- vlsi/hammer | 2 +- vlsi/hammer-cadence-plugins | 2 +- 5 files changed, 56 insertions(+), 58 deletions(-) diff --git a/vlsi/example-vlsi b/vlsi/example-vlsi index 21ff9598..f853a1ed 100755 --- a/vlsi/example-vlsi +++ b/vlsi/example-vlsi @@ -24,7 +24,7 @@ def example_tool_settings(x: hammer_vlsi.HammerTool) -> bool: x.append(''' # TODO # Place custom TCL here -set_db route_design_bottom_routing_layer 1 +set_db route_design_bottom_routing_layer 2 set_db route_design_top_routing_layer 7 ''') return True diff --git a/vlsi/extra_libraries/example/ExampleDCO.gds b/vlsi/extra_libraries/example/ExampleDCO.gds index 556f117ced6baa701af624cb5670c1bafdc0e7fe..4864e115aa2875efd1cc3ceb0dbabe47dda18668 100644 GIT binary patch literal 8556 zcmbuEUuf1<7{{OY_4T(gr_MC<1(O-{2aBA}(!q*ZQz$_rB}J1>x3^lo_Ks;O81xGa zGBElB1{o++Xi$+|b@^UJmtA)g{kiI@`)+!kbN0#O&(ra=9XNjGch8s4&h|U=63=o8Vo;{74>4*nPVqr+pX~@_sNrUNven_rN`kA8#$)o+izs}i3nx*$ca%Ixb96d-L?Fat#>b12&x1Ar7E0cca=t1&m zKk#pKc9DBZ?}y~dq@Ou@kUZKC{P(KY*8RHe{E%Fk^fN~fl1KZ2f0MI|JXm@^Bv&T= z%+Z77(SG26SiQD}bldqMxiaZzjvgeB_5=U0vx{siy&sY*lYZvtLGoxn@NZYItr6XJ zen_rN`kA8#$)o+iKkDovkComJ$(2bzbMzp2v>*7#)NAVr-FALRu1xxwqX)^O{lLG= z*+q7j-Ve!@Nk4P+AbGSO_@7d*tv$N!{E%Fk^fN~fl1KZ2f3LHP>?^$=k}H#b=IBB4 zXg}~jt6p0NbldqMxiaZzjvgeB_5=SxXBRnCdOsvrCjHFOgXGbE;6I{XTSs-<`60P7 z>1U1}B#-t3|D?%v9V@*bPFkpI@;2w!&$~qrk}Gfh`UC%TDQ>->f7Qth0-}QF=clS0??;(SzjCe&Byo zy|&)cZRdyN%A}t;dXPNY5B%qxUF7Z3`ysh9>1U1}B#-t3|2yin^{#F^KO|Qs{mjvW z*6CP_M0zbldqMxiaZzjvgeB_5=S#XBYXn^nOUL zO!}Fl2g#%T!2gMQZGEcS&JW3zNk4P+AbGSO_%A!V$d%IjA-OW?XO12ukM;xqXX>@} zg>E}PBv&T=%+Z77(SG2+=IkP0mfjD^l}SHy^dNb(ANapgudQ!%+xa26GU;cI9wd+U z1OIhr7x}LAen_rN`kA8#$)kPmul+JB_Wqya68-RxLHGWjBf0Xw{0r%C4c~uU_LJ0p z?ur=yoD^9(bc5u|(C_>6ufG=Dpa1?BUGF!Vzi;pc&2M?iKmU0*m)T$K&foCwpW5?g zOKBeaenN8h=~X(?>)*d!v&jC2MfUys#|!`Z{m*aV{n15!{ks?0e`b;W!wc>A|NH*^ z+PXdz#a%U7D*g5@zWy(Q)W@W+SxnEIdZ{(%?@M~V=*mE|nCqOLIN54X96vI2G^e#} z?B>>%tk%kkYim|(O~o~w)mm3^ZOdxiU2#2<)!JBbJ(|_Juj1OC)!I~X?Z|3vuDC|B zTEktrBYZZt=);lobnF5W!>`hev0c2<4*h~)HkRek!9Fsqt zyQxn5f8DkH?q_$Sm3P+;R$O^^?fHr;@2*W&TzPk`RdMCrwV8@5@2^J74u>-n9!|S=%h8I@7I*xz>xXwU3?Z z%-KISIrrwnu}C-boEKx>%(GsKc{9&@Ip)p${qlLtoB2EDTFk4LBXZa@wCK&WjL+77T!D7}FN>FK%qRFP)TUoQov=j_Ffk6g_ z6&PgTpdy2c?5fLMb=`HBb=OsNSvP%u@7c#4ACG5e+YcT;_I-a}KJVF{$6j7nxn}dQ zTis}O{^{;sG{ncT1Yp?(@e_ogQuVKfm8CU$F4mU6;1){q@_wcl7_VapKyM zgKqW0OuLHP9gCc+?rXZoUA3g?oO^QV0{y9J_%@vVXZM7=MRKv@e&=rQ|2NNm zb^73k_`5^^4fIivhzc7G3#fK9wblpBY(HaHA{W)Lvk_eXOA8vPxd4K zGI?!Q=(6)eaxv>?j~*mX_9Oo)lWTf>@I!Jj>t~N1Bv1Au|7v+{*66bHLvk_eXOA8v zPxd4KT9a!Y_Q4Oy#jKw_dXPNXkNl6wYx9^cJ3k~BvwrsILGolj@~<KO`5ke)i}=@?<~q_sMJXoGv>*Bp0)O_UJ+KWIyunHo0bx z4}M54X8r8ZgXGD6xazt7~F{XY01xtR5{M-P%G`;q@8 zd2J5rvhzc7G3#fK9wblpBmW_jYYzM1hvZ_`&mKKUp6o~dqw?Au(`Dy}_`3~d2NpS;DPh7W#7F5cOXK7X@E50WSQ(fLowYcr86{p`_$Ie@|YU_jTF% zA-S0Kvquk-C;O5AqRBNM_~3`+V%Eaz1gaxv>?j~*mX_9OpwlWQh?@I!Jj>t~N1Bv1Au|5x(be51?G56Q)>pFMhz zJlT)@H%zYi&Idmv7qfo$=t1&iKk|Psug#CT?EH{i%=+1*2g#HD$bZx1nxB2}Lvk_e zXOA8vPxgbq@z+rM`@c39=&%3keZYoyynZ)7ug|8xIsX3fiPNs}`=oP5doSw`Op{!U z{h>eg`Df1ksh|IbpMu|L{@yFoH2>7=clFPqzpQ=!j`01d-ETIc{T%E)KyqX3Up~+N zntAra_s4U8|KayH_x{d#zW+V*>>rqC|HxeXUAMl!U)j_>Q9amj3tg9ei{JU1bIm@t zxThL9dG__zc(`Bk`_-gd+Ea~>of|yU8XY`wwD(v^>)yWGTbqhn-8I+dqSo@7YfDjU zRn4`vsP$0I^;A)7ZO!#`QR~r~YgNhQ~%)gX68&-X1-Ec5K}KXH)XreA<`j7M}BJ z%3FBWYbkHxd9SCuh5x>Mo$?m`8*?M&)k9M9bN(Ua)uU3 Date: Thu, 3 Oct 2019 01:52:36 +0000 Subject: [PATCH 38/61] [firechip] Remove SimConfigs --- .../firechip/src/main/scala/SimConfigs.scala | 42 ------------------- 1 file changed, 42 deletions(-) delete mode 100644 generators/firechip/src/main/scala/SimConfigs.scala diff --git a/generators/firechip/src/main/scala/SimConfigs.scala b/generators/firechip/src/main/scala/SimConfigs.scala deleted file mode 100644 index 06e6aa93..00000000 --- a/generators/firechip/src/main/scala/SimConfigs.scala +++ /dev/null @@ -1,42 +0,0 @@ -//See LICENSE for license details. -package firesim.firesim - -import freechips.rocketchip.config.{Parameters, Config, Field} - -import midas.models._ - -import firesim.endpoints._ -import firesim.configs._ - -/******************************************************************************* -* Full PLATFORM_CONFIG Configurations. These set simulator parameters. -* -* In general, if you're adding or removing features from any of these, you -* should CREATE A NEW ONE, WITH A NEW NAME. This is because the manager -* will store this name as part of the tags for the AGFI, so that later you can -* reconstruct what is in a particular AGFI. These tags are also used to -* determine which driver to build. -*******************************************************************************/ -class FireSimConfig extends Config(new BasePlatformConfig) - -class FireSimClockDivConfig extends Config( - new FireSimConfig) - -class FireSimDDR3Config extends Config( - new FireSimConfig) - -class FireSimDDR3LLC4MBConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSLLC4MBConfig extends Config( - new FireSimConfig) - -class FireSimDDR3FRFCFSLLC4MB3ClockDivConfig extends Config( - new FireSimConfig) - -class Midas2Config extends Config( - new WithMultiCycleRamModels ++ - new FireSimConfig) From 5845862525d69cf14db1c9fb634ed335962bb4c7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 3 Oct 2019 02:28:48 +0000 Subject: [PATCH 39/61] [Firechip] Push FASED configs into TargetConfigs.scala --- generators/firechip/src/main/scala/TargetConfigs.scala | 7 ++++++- .../firechip/src/test/scala/ScalaTestSuite.scala | 10 +++++----- 2 files changed, 11 insertions(+), 6 deletions(-) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d88ffa25..d0c55ed3 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -20,7 +20,7 @@ import icenet._ import firesim.endpoints._ import firesim.util.{WithNumNodes} -import firesim.configs.WithDefaultMemModel +import firesim.configs._ class WithBootROM extends Config((site, here, up) => { case BootROMParams => { @@ -86,6 +86,11 @@ class WithScalaTestFeatures extends Config((site, here, up) => { case PrintTracePort => true }) +// FASED Config Aliases. This to enable config generation via "_" concatenation +// which requires that all config classes be defined in the same package +class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB +class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 77415636..49737be4 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -130,10 +130,10 @@ abstract class FireSimTestSuite( runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipConfig", "FireSimConfig") -class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "FireSimConfig") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig", "FireSimConfig") { +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } -class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "Midas2Config") -class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "Midas2Config") +class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") +class RamModelBoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig", "BaseF1Config_MCRams") From 7c0bb51242e1a9915c16934edfbdd886537c9fb1 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 18:15:34 +0000 Subject: [PATCH 40/61] [firechip] Update scalatest suite --- generators/firechip/src/test/scala/ScalaTestSuite.scala | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index 49737be4..e7194d8c 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -130,9 +130,9 @@ abstract class FireSimTestSuite( runSuite("verilator")(FastBlockdevTests) } -class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipQuadCoreConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "FireSimBoomConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") -class RocketNICF1Tests extends FireSimTestSuite("FireSim", "FireSimRocketChipConfig_DDR3FRFCFSLLC4MB", "BaseF1Config") { +class RocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "DDR3FRFCFSLLC4MB_FireSimRocketChipQuadCoreConfig", "BaseF1Config") +class BoomF1Tests extends FireSimTestSuite("FireBoomNoNIC", "DDR3FRFCFSLLC4MB_FireSimBoomConfig", "BaseF1Config") +class RocketNICF1Tests extends FireSimTestSuite("FireSim", "DDR3FRFCFSLLC4MB_FireSimRocketChipConfig", "BaseF1Config") { runSuite("verilator")(NICLoopbackTests) } class RamModelRocketF1Tests extends FireSimTestSuite("FireSimNoNIC", "FireSimRocketChipDualCoreConfig", "BaseF1Config_MCRams") From 39172e0d385f40763bbff217a1d99351c0b14240 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 18:27:19 +0000 Subject: [PATCH 41/61] [CI] Update FireSim defaults --- .circleci/defaults.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 8497f304..f5387bd8 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" -mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" -mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" +mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" +mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" From 6210ca2df870fc13f147bf417dc4525b72b254fc Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 21:03:16 +0000 Subject: [PATCH 42/61] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 26ffba7c..4c1a3aa2 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 26ffba7cbca2982fef6b221a7abbc51d5cdc4b62 +Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 From 36b269bfc9aa8582150abb5011f1c5e60a7e00e2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Fri, 4 Oct 2019 21:51:39 +0000 Subject: [PATCH 43/61] [CI] Fix PLATFORM_CONFIG in firesim --- .circleci/defaults.sh | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index f5387bd8..bdc53e80 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,6 +47,6 @@ mapping["boom"]="SUB_PROJECT=example CONFIG=SmallBoomConfig" mapping["rocketchip"]="SUB_PROJECT=rocketchip" mapping["blockdevrocketchip"]="SUB_PROJECT=example CONFIG=SimBlockDeviceRocketConfig TOP=TopWithBlockDevice" mapping["hwacha"]="SUB_PROJECT=example CONFIG=HwachaRocketConfig GENERATOR_PACKAGE=hwacha" -mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimConfig" -mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=FireSimConfig" -mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=FireSimClockDivConfig" +mapping["firesim"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" +mapping["fireboom"]="DESIGN=FireBoom TARGET_CONFIG=DDR3FRFCFSLLC4MB_FireSimBoomConfig PLATFORM_CONFIG=BaseF1Config" +mapping["firesim-clockdiv"]="DESIGN=FireSim TARGET_CONFIG=DDR3FRFCFSLLC4MB3Div_FireSimRocketChipConfig PLATFORM_CONFIG=BaseF1Config" From 53f58f6baa21f2cf2c818f0cdbea8004f181d23e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Wed, 25 Sep 2019 15:41:21 -0700 Subject: [PATCH 44/61] Support serializable endpoints; Golden Gate stage --- build.sbt | 1 + .../firechip/src/main/scala/EndpointBinders.scala | 10 +++------- generators/firechip/src/main/scala/Generator.scala | 9 +++++---- .../firechip/src/test/scala/ScalaTestSuite.scala | 5 +++-- sims/firesim | 2 +- vlsi/hammer | 2 +- 6 files changed, 14 insertions(+), 15 deletions(-) diff --git a/build.sbt b/build.sbt index 4d747829..ccc9e87f 100644 --- a/build.sbt +++ b/build.sbt @@ -23,6 +23,7 @@ lazy val commonSettings = Seq( addCompilerPlugin("org.scalamacros" % "paradise" % "2.1.0" cross CrossVersion.full), unmanagedBase := (chipyardRoot / unmanagedBase).value, allDependencies := allDependencies.value.filterNot(_.organization == "edu.berkeley.cs"), + exportJars := true, resolvers ++= Seq( Resolver.sonatypeRepo("snapshots"), Resolver.sonatypeRepo("releases"), diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/EndpointBinders.scala index 0450f8f3..cc76503d 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/EndpointBinders.scala @@ -14,8 +14,7 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.widgets.{IsEndpoint} -import midas.models.{FASEDEndpoint, FasedAXI4Edge} +import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} import firesim.endpoints._ import firesim.configs.MemModelKey import firesim.util.RegisterEndpointBinder @@ -55,11 +54,8 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - val fasedP = p.alterPartial({ - case NastiKey => nastiKey - case FasedAXI4Edge => Some(edge) - }) - FASEDEndpoint(axi4Bundle, t.reset.toBool, p(MemModelKey)(fasedP))(fasedP) + FASEDEndpoint(axi4Bundle, t.reset.toBool, + CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) diff --git a/generators/firechip/src/main/scala/Generator.scala b/generators/firechip/src/main/scala/Generator.scala index 169cbe1f..0c5b4909 100644 --- a/generators/firechip/src/main/scala/Generator.scala +++ b/generators/firechip/src/main/scala/Generator.scala @@ -2,7 +2,7 @@ package firesim.firesim -import java.io.{File} +import java.io.{File, FileWriter} import chisel3.experimental.RawModule import chisel3.internal.firrtl.{Circuit, Port} @@ -48,13 +48,14 @@ trait IsFireSimGeneratorLike extends HasFireSimGeneratorUtilities with HasTestSu } object FireSimGenerator extends App with IsFireSimGeneratorLike { + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs lazy val generatorArgs = GeneratorArgs(args) lazy val genDir = new File(names.targetDir) - elaborateAndCompileWithMidas + // The only reason this is not generateFirrtl; generateAnno is that we need to use a different + // JsonProtocol to properly write out the annotations. Fix once the generated are unified + elaborate generateTestSuiteMakefrags - generateHostVerilogHeader generateArtefacts - generateTclEnvFile } // For now, provide a separate generator app when not specifically building for FireSim diff --git a/generators/firechip/src/test/scala/ScalaTestSuite.scala b/generators/firechip/src/test/scala/ScalaTestSuite.scala index e7194d8c..0cda4b93 100644 --- a/generators/firechip/src/test/scala/ScalaTestSuite.scala +++ b/generators/firechip/src/test/scala/ScalaTestSuite.scala @@ -23,6 +23,8 @@ abstract class FireSimTestSuite( import scala.concurrent.duration._ import ExecutionContext.Implicits.global + val longName = names.topModuleProject + "." + names.topModuleClass + "." + names.configs + lazy val generatorArgs = GeneratorArgs( midasFlowKind = "midas", targetDir = "generated-src", @@ -42,7 +44,6 @@ abstract class FireSimTestSuite( val commonMakeArgs = Seq(s"DESIGN=${generatorArgs.topModuleClass}", s"TARGET_CONFIG=${generatorArgs.targetConfigs}", s"PLATFORM_CONFIG=${generatorArgs.platformConfigs}") - override lazy val platform = hostParams(midas.Platform) def invokeMlSimulator(backend: String, name: String, debug: Boolean, additionalArgs: Seq[String] = Nil) = { make((Seq(s"${outDir.getAbsolutePath}/${name}.%s".format(if (debug) "vpd" else "out"), @@ -122,7 +123,7 @@ abstract class FireSimTestSuite( clean mkdirs - elaborateAndCompileWithMidas + elaborate generateTestSuiteMakefrags runTest("verilator", "rv64ui-p-simple", false, Seq(s"""EXTRA_SIM_ARGS=+trace-test-output0""")) diffTracelog("rv64ui-p-simple.out") diff --git a/sims/firesim b/sims/firesim index 4c1a3aa2..a94bea1d 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 +Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a diff --git a/vlsi/hammer b/vlsi/hammer index 1b07b9a3..a27886fb 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 +Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 From 95a44ff6d06186d0bdaa72cb308b0bc37be76d93 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 17:54:33 -0400 Subject: [PATCH 45/61] Switch to bash optarg for cli handling in init-submodules script --- scripts/init-submodules-no-riscv-tools.sh | 24 +++++++++++++++-------- 1 file changed, 16 insertions(+), 8 deletions(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index da34adf0..34b9ed8d 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -6,17 +6,24 @@ set -o pipefail RDIR=$(git rev-parse --show-toplevel) -NO_FIRESIM=false +_usage() { + echo "usage: ${0} [--no-firesim]" >&2 + exit 1 +} -while test $# -gt 0 -do - case "$1" in - --no-firesim) - NO_FIRESIM=true; - ;; +NO_FIRESIM=false +while getopts 'h-:' opt ; do + case ${opt} in + -) + case ${OPTARG} in + no-firesim) NO_FIRESIM=true ;; + *) echo "invalid option: --${OPTARG}" >&2 ; _usage ;; + esac ;; + h) _usage ;; + *) echo "invalid option: -${opt}" >&2 ; _usage ;; esac - shift done +shift $((OPTIND - 1)) # Ignore toolchain submodules cd "$RDIR" @@ -39,6 +46,7 @@ git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update if [ $NO_FIRESIM = false ]; then +echo "initializing firesim" # Renable firesim and init only the required submodules to provide # all required scala deps, without doing a full build-setup git config --unset submodule.sims/firesim.update From 8e8ce09ce92e239920732ee2352ef24f43074436 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 19:04:08 -0400 Subject: [PATCH 46/61] Move qemu to chipyard from firesim --- .gitmodules | 3 +++ scripts/build-toolchains.sh | 3 +++ scripts/init-submodules-no-riscv-tools.sh | 2 ++ sims/firesim | 2 +- toolchains/qemu | 1 + 5 files changed, 10 insertions(+), 1 deletion(-) create mode 160000 toolchains/qemu diff --git a/.gitmodules b/.gitmodules index 4c23765e..2f4d9eb3 100644 --- a/.gitmodules +++ b/.gitmodules @@ -92,3 +92,6 @@ [submodule "vlsi/hammer-mentor-plugins"] path = vlsi/hammer-mentor-plugins url = git@github.com:ucb-bar/hammer-mentor-plugins.git +[submodule "toolchains/qemu"] + path = toolchains/qemu + url = https://github.com/qemu/qemu.git diff --git a/scripts/build-toolchains.sh b/scripts/build-toolchains.sh index 738b5ae7..cde56227 100755 --- a/scripts/build-toolchains.sh +++ b/scripts/build-toolchains.sh @@ -121,6 +121,9 @@ cp -p "${SRCDIR}/riscv-isa-sim/build/libfesvr.a" "${RISCV}/lib/" CC= CXX= module_all riscv-pk --prefix="${RISCV}" --host=riscv64-unknown-elf module_all riscv-tests --prefix="${RISCV}/riscv64-unknown-elf" +# Common tools (not in any particular toolchain dir) +SRCDIR="$RDIR/toolchains" module_all qemu --prefix="${RISCV}" --target-list=riscv64-softmmu + cd "$RDIR" { diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 34b9ed8d..8f90f2d1 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -30,6 +30,8 @@ cd "$RDIR" for name in toolchains/*/*/ ; do git config submodule."${name%/}".update none done +git config submodule.toolchains.qemu.update none + # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none # Disable updates to the hammer tool plugins repos diff --git a/sims/firesim b/sims/firesim index ffe68ac7..1e7f304c 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit ffe68ac7f69795b2cccf7d9510facd5e2db4edc6 +Subproject commit 1e7f304c49507b46cf77ccf5d21a807db633f35c diff --git a/toolchains/qemu b/toolchains/qemu new file mode 160000 index 00000000..4f591025 --- /dev/null +++ b/toolchains/qemu @@ -0,0 +1 @@ +Subproject commit 4f59102571fce49af180cfc6d4cdd2b5df7bdb14 From 3e2fba51505f470735adb11c4d8552ba1fd4dcd3 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Fri, 4 Oct 2019 19:06:47 -0400 Subject: [PATCH 47/61] Update firesim to a version that has this chipyard submoduled. --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 1e7f304c..3840b6e7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 1e7f304c49507b46cf77ccf5d21a807db633f35c +Subproject commit 3840b6e7bfab7ad954d9494cf732cf99e0d86dc2 From f040db83c967d8f7f494d83dffc85705ac372b96 Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Fri, 4 Oct 2019 16:38:59 -0700 Subject: [PATCH 48/61] toolchains: Bump esp-isa-sim This fixes the libhwacha.so build. --- toolchains/esp-tools/riscv-isa-sim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/toolchains/esp-tools/riscv-isa-sim b/toolchains/esp-tools/riscv-isa-sim index 92f2f467..0ffa02e5 160000 --- a/toolchains/esp-tools/riscv-isa-sim +++ b/toolchains/esp-tools/riscv-isa-sim @@ -1 +1 @@ -Subproject commit 92f2f467c00caa991379ba55ece7118f068c2218 +Subproject commit 0ffa02e5b4ca57ec44684119a1a9a31b3871857b From 151d3f16c3260a00e427372b9dd866e32d9b9e68 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sat, 5 Oct 2019 00:24:31 +0000 Subject: [PATCH 49/61] typo in command for ignoring qemu submodule --- scripts/init-submodules-no-riscv-tools.sh | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/scripts/init-submodules-no-riscv-tools.sh b/scripts/init-submodules-no-riscv-tools.sh index 8f90f2d1..0ce30475 100755 --- a/scripts/init-submodules-no-riscv-tools.sh +++ b/scripts/init-submodules-no-riscv-tools.sh @@ -30,7 +30,7 @@ cd "$RDIR" for name in toolchains/*/*/ ; do git config submodule."${name%/}".update none done -git config submodule.toolchains.qemu.update none +git config submodule.toolchains/qemu.update none # Disable updates to the FireSim submodule until explicitly requested git config submodule.sims/firesim.update none @@ -43,6 +43,8 @@ git submodule update --init --recursive #--jobs 8 for name in toolchains/*/*/ ; do git config --unset submodule."${name%/}".update done +git config --unset submodule.toolchains/qemu.update + git config --unset submodule.vlsi/hammer-cadence-plugins.update git config --unset submodule.vlsi/hammer-synopsys-plugins.update git config --unset submodule.vlsi/hammer-mentor-plugins.update From ad76e0ad1c735862e49f3009d54f82f006721e71 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Thu, 3 Oct 2019 15:56:05 -0700 Subject: [PATCH 50/61] Bump FireSim; Revert an errant hammer bump --- sims/firesim | 2 +- vlsi/hammer | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/sims/firesim b/sims/firesim index a94bea1d..9bd6679e 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit a94bea1d16e858c4b04d03306fb100962b09dc9a +Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 diff --git a/vlsi/hammer b/vlsi/hammer index a27886fb..1b07b9a3 160000 --- a/vlsi/hammer +++ b/vlsi/hammer @@ -1 +1 @@ -Subproject commit a27886fb42c121f3ba5f684acaf5856b2ec293e1 +Subproject commit 1b07b9a378c2936389b95f7ee1436e1f492d55e2 From 370c0dbfa88ce8e79c9c61cf41911d06580c3ac2 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sat, 5 Oct 2019 21:16:31 +0000 Subject: [PATCH 51/61] Bump FireSim [ci skip] --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 4c1a3aa2..31682ca9 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 4c1a3aa2122d35c505e8135642bfb6870f2fce19 +Subproject commit 31682ca9957ea20a823ab313285b1a95a6dfeb80 From aa6e09f80056852e52a4a9d21161f558ebeb90f8 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:32:50 +0000 Subject: [PATCH 52/61] Rename Endpoint -> Bridge --- .../FPGA-Accelerated-Simulators.rst | 2 +- ...pointBinders.scala => BridgeBinders.scala} | 48 +++++++++---------- .../src/main/scala/TargetConfigs.scala | 6 +-- .../src/main/scala/TargetMixins.scala | 4 +- 4 files changed, 30 insertions(+), 30 deletions(-) rename generators/firechip/src/main/scala/{EndpointBinders.scala => BridgeBinders.scala} (52%) diff --git a/docs/Simulation/FPGA-Accelerated-Simulators.rst b/docs/Simulation/FPGA-Accelerated-Simulators.rst index 29f42880..c8640f9d 100644 --- a/docs/Simulation/FPGA-Accelerated-Simulators.rst +++ b/docs/Simulation/FPGA-Accelerated-Simulators.rst @@ -87,4 +87,4 @@ will look as follows: You should then be able to refer to those classes or an alias of them in your ``DESIGN`` or ``TARGET_CONFIG`` variables. Note that if your target machine has I/O not provided in the default FireChip targets (see ``generators/firechip/src/main/scala/Targets.scala``) you may need -to write a custom endpoint. +to write a custom bridge. diff --git a/generators/firechip/src/main/scala/EndpointBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala similarity index 52% rename from generators/firechip/src/main/scala/EndpointBinders.scala rename to generators/firechip/src/main/scala/BridgeBinders.scala index cc76503d..c2bed0e5 100644 --- a/generators/firechip/src/main/scala/EndpointBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -14,12 +14,12 @@ import testchipip.{HasPeripherySerialModuleImp, HasPeripheryBlockDeviceModuleImp import icenet.HasPeripheryIceNICModuleImpValidOnly import junctions.{NastiKey, NastiParameters} -import midas.models.{FASEDEndpoint, AXI4EdgeSummary, CompleteConfig} -import firesim.endpoints._ +import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig} +import firesim.bridges._ import firesim.configs.MemModelKey -import firesim.util.RegisterEndpointBinder +import firesim.util.RegisterBridgeBinder -class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripheryDebugModuleImp => +class WithTiedOffDebug extends RegisterBridgeBinder({ case target: HasPeripheryDebugModuleImp => target.debug.clockeddmi.foreach({ cdmi => cdmi.dmi.req.valid := false.B cdmi.dmi.req.bits := DontCare @@ -30,23 +30,23 @@ class WithTiedOffDebug extends RegisterEndpointBinder({ case target: HasPeripher Seq() }) -class WithSerialEndpoint extends RegisterEndpointBinder({ - case target: HasPeripherySerialModuleImp => Seq(SerialEndpoint(target.serial)(target.p)) +class WithSerialBridge extends RegisterBridgeBinder({ + case target: HasPeripherySerialModuleImp => Seq(SerialBridge(target.serial)(target.p)) }) -class WithNICEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICEndpoint(target.net)(target.p)) +class WithNICBridge extends RegisterBridgeBinder({ + case target: HasPeripheryIceNICModuleImpValidOnly => Seq(NICBridge(target.net)(target.p)) }) -class WithUARTEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTEndpoint(u)(target.p)) +class WithUARTBridge extends RegisterBridgeBinder({ + case target: HasPeripheryUARTModuleImp => target.uart.map(u => UARTBridge(u)(target.p)) }) -class WithBlockDeviceEndpoint extends RegisterEndpointBinder({ - case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevEndpoint(target.bdev, target.reset.toBool)(target.p)) +class WithBlockDeviceBridge extends RegisterBridgeBinder({ + case target: HasPeripheryBlockDeviceModuleImp => Seq(BlockDevBridge(target.bdev, target.reset.toBool)(target.p)) }) -class WithFASEDEndpoint extends RegisterEndpointBinder({ +class WithFASEDBridge extends RegisterBridgeBinder({ case t: CanHaveMasterAXI4MemPortModuleImp => implicit val p = t.p (t.mem_axi4 zip t.outer.memAXI4Node).flatMap({ case (io, node) => @@ -54,23 +54,23 @@ class WithFASEDEndpoint extends RegisterEndpointBinder({ val nastiKey = NastiParameters(axi4Bundle.r.bits.data.getWidth, axi4Bundle.ar.bits.addr.getWidth, axi4Bundle.ar.bits.id.getWidth) - FASEDEndpoint(axi4Bundle, t.reset.toBool, + FASEDBridge(axi4Bundle, t.reset.toBool, CompleteConfig(p(firesim.configs.MemModelKey), nastiKey, Some(AXI4EdgeSummary(edge)))) }) }).toSeq }) -class WithTracerVEndpoint extends RegisterEndpointBinder({ - case target: HasTraceIOImp => TracerVEndpoint(target.traceIO)(target.p) +class WithTracerVBridge extends RegisterBridgeBinder({ + case target: HasTraceIOImp => TracerVBridge(target.traceIO)(target.p) }) -// Shorthand to register all of the provided endpoints above -class WithDefaultFireSimEndpoints extends Config( +// Shorthand to register all of the provided bridges above +class WithDefaultFireSimBridges extends Config( new WithTiedOffDebug ++ - new WithSerialEndpoint ++ - new WithNICEndpoint ++ - new WithUARTEndpoint ++ - new WithBlockDeviceEndpoint ++ - new WithFASEDEndpoint ++ - new WithTracerVEndpoint + new WithSerialBridge ++ + new WithNICBridge ++ + new WithUARTBridge ++ + new WithBlockDeviceBridge ++ + new WithFASEDBridge ++ + new WithTracerVBridge ) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index d0c55ed3..689927b0 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -18,7 +18,7 @@ import scala.math.{min, max} import tracegen.TraceGenKey import icenet._ -import firesim.endpoints._ +import firesim.bridges._ import firesim.util.{WithNumNodes} import firesim.configs._ @@ -113,7 +113,7 @@ class FireSimRocketChipConfig extends Config( new WithPerfCounters ++ new WithoutClockGating ++ new WithDefaultMemModel ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.DefaultConfig) class WithNDuplicatedRocketCores(n: Int) extends Config((site, here, up) => { @@ -163,7 +163,7 @@ class FireSimBoomConfig extends Config( new WithDefaultMemModel ++ new boom.common.WithLargeBooms ++ new boom.common.WithNBoomCores(1) ++ - new WithDefaultFireSimEndpoints ++ + new WithDefaultFireSimBridges ++ new freechips.rocketchip.system.BaseConfig ) diff --git a/generators/firechip/src/main/scala/TargetMixins.scala b/generators/firechip/src/main/scala/TargetMixins.scala index 0c7d2eb9..43d03853 100644 --- a/generators/firechip/src/main/scala/TargetMixins.scala +++ b/generators/firechip/src/main/scala/TargetMixins.scala @@ -11,12 +11,12 @@ import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.util._ import freechips.rocketchip.subsystem._ import freechips.rocketchip.rocket.TracedInstruction -import firesim.endpoints.{TraceOutputTop, DeclockedTracedInstruction} +import firesim.bridges.{TraceOutputTop, DeclockedTracedInstruction} import midas.targetutils.{ExcludeInstanceAsserts, MemModelAnnotation} /* Wires out tile trace ports to the top; and wraps them in a Bundle that the - * TracerV endpoint can match on. + * TracerV bridge can match on. */ object PrintTracePort extends Field[Boolean](false) From 115102c987f9400bead34d99808ffcbb9050c91d Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 03:36:12 +0000 Subject: [PATCH 53/61] Bump FireSim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 9bd6679e..a1f3a927 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 9bd6679ea8d3f7d3e99e827d1cd27322d7b498b1 +Subproject commit a1f3a927a975dea1200a56260c140998866a1c51 From 577cede749089b0290e6e6bd31f9b491e4b293cd Mon Sep 17 00:00:00 2001 From: Albert Ou Date: Sat, 5 Oct 2019 01:08:59 -0700 Subject: [PATCH 54/61] sha3: Bump for RTL fixes/optimizations --- generators/sha3 | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/sha3 b/generators/sha3 index b364cd36..e6f5bab6 160000 --- a/generators/sha3 +++ b/generators/sha3 @@ -1 +1 @@ -Subproject commit b364cd367ceb8636b8dbec3c46bf1aab1788b2c3 +Subproject commit e6f5bab675bfdad0ebdc23239adbd52ca89706e6 From 427082ba7096a9d9cc2ad90c96faeaa39bdfac01 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 6 Oct 2019 14:28:03 -0700 Subject: [PATCH 55/61] [skip ci] address John's comments --- docs/VLSI/Tutorial.rst | 6 +++--- vlsi/example.yml | 1 + 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index de6e0166..db1cee60 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -54,7 +54,7 @@ Prerequisites * Genus, Innovus, and Calibre licenses * For ASAP7 specifically: - * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin will extract and setup the PDK for you into a cache directory. + * Download the `ASAP7 PDK `__ tarball to a directory of choice but do not extract it. The tech plugin is configured to extract the PDK into a cache directory for you. * If you have additional ASAP7 hard macros, their LEF & GDS need to be 4x upscaled @ 4000 DBU precision. They may live outside ``extra_libraries`` at your discretion. * Innovus version must be >= 15.2 or <= 18.1 (ISRs excluded). @@ -84,7 +84,7 @@ To elaborate the ``Sha3RocketConfig`` (Rocket Chip w/ the accelerator) and set u make buildfile MACROCOMPILER_MODE='--mode synflops' CONFIG=Sha3RocketConfig VLSI_TOP=Sha3AccelwBB -The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler. Therefore, flip-flop arrays are used instead. Note this will dramatically increase synthesis runtimes if your design has a lot of caches. +The ``MACROCOMPILER_MODE='--mode synflops'`` is needed because the ASAP7 process does not yet have a memory compiler, so flip-flop arrays are used instead. This will dramatically increase the synthesis runtime if your design has a lot of memory state (e.g. large caches). The ``CONFIG=Sha3RocketConfig`` selects the target generator config in the same manner as the rest of the Chipyard framework. This elaborates a Rocket Chip with the Sha3Accel module. @@ -99,7 +99,7 @@ example-vlsi ^^^^^^^^^^^^ This is the entry script with placeholders for hooks. In the ``ExampleDriver`` class, a list of hooks is passed in the ``get_extra_par_hooks``. Hooks are additional snippets of python and TCL (via ``x.append()``) to extend the Hammer APIs. Hooks can be inserted using the ``make_pre/post/replacement_hook`` methods as shown in this example. Refer to the Hammer documentation on hooks for a detailed description of how these are injected into the VLSI flow. -The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter. This hook is run after ``write_design`` because the ASAP7 PDK requires post-par GDSs to be scaled down by a factor of 4. +The ``scale_final_gds`` hook is a particularly powerful hook. It dumps a Python script provided by the ASAP7 tech plugin, an executes it within the Innovus TCL interpreter, and should be inserted after ``write_design``. This hook is necessary because the ASAP7 PDK does place-and-route using 4x upscaled LEFs for Innovus licensing reasons, thereby requiring the cells created in the post-P&R GDS to be scaled down by a factor of 4. example.yml ^^^^^^^^^^^ diff --git a/vlsi/example.yml b/vlsi/example.yml index 024e844f..c8e4a72b 100644 --- a/vlsi/example.yml +++ b/vlsi/example.yml @@ -38,6 +38,7 @@ par.generate_power_straps_options: - M9 track_width: 7 # minimum allowed for M2 & M3 track_spacing: 0 + track_spacing_M3: 1 # to avoid M2 shorts at higher density track_start: 10 power_utilization: 0.05 power_utilization_M8: 1.0 From e0b4f21ce6d907aed13076afc74e5ba5e4f3a107 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 18:46:22 -0400 Subject: [PATCH 56/61] fixup circular reference with firesim --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 6d578eeb..226df1d6 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 6d578eeb40b6da88e192d0ab4844b3ac690868f3 +Subproject commit 226df1d6134aca22e1e1592935b0b8033f8e0734 From 9f42db804cd15b7b54c3346562d2b6ab00f5043e Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Sun, 6 Oct 2019 22:49:35 +0000 Subject: [PATCH 57/61] [FireChip] Add an alias for L2 Config Mixins --- generators/firechip/src/main/scala/TargetConfigs.scala | 3 +++ 1 file changed, 3 insertions(+) diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala index 689927b0..c91ae05e 100644 --- a/generators/firechip/src/main/scala/TargetConfigs.scala +++ b/generators/firechip/src/main/scala/TargetConfigs.scala @@ -91,6 +91,9 @@ class WithScalaTestFeatures extends Config((site, here, up) => { class DDR3FRFCFSLLC4MB extends FRFCFS16GBQuadRankLLC4MB class DDR3FRFCFSLLC4MB3Div extends FRFCFS16GBQuadRankLLC4MB3Div +// L2 Config Aliases. For use with "_" concatenation +class L2SingleBank512K extends freechips.rocketchip.subsystem.WithInclusiveCache + /******************************************************************************* * Full TARGET_CONFIG configurations. These set parameters of the target being * simulated. From c7cba24bf608219328ff3a586c29a41fc43e976b Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 19:13:40 -0400 Subject: [PATCH 58/61] Add qemu to CI rules for rebuilding toolchain --- .circleci/create-hash.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/create-hash.sh b/.circleci/create-hash.sh index 63dfa242..939eeb31 100755 --- a/.circleci/create-hash.sh +++ b/.circleci/create-hash.sh @@ -15,7 +15,7 @@ cd $LOCAL_CHIPYARD_DIR # Use normalized output of git-submodule status as hashfile for tools in 'riscv-tools' 'esp-tools' ; do - git submodule status "toolchains/${tools}" | while read -r line ; do + git submodule status "toolchains/${tools}" "toolchains/qemu" | while read -r line ; do echo "${line#[!0-9a-f]}" done > "${HOME}/${tools}.hash" done From 0d84e3646e339d5e4b07fdbbb89abb6a19a73329 Mon Sep 17 00:00:00 2001 From: Nathan Pemberton Date: Sun, 6 Oct 2019 23:38:46 -0400 Subject: [PATCH 59/61] adds sha3 workload to firemarshal --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 226df1d6..22ce787f 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 226df1d6134aca22e1e1592935b0b8033f8e0734 +Subproject commit 22ce787fab2515c81bfbc98bbfdcd94b075d7a8a From 79f3776966460ebc5dd8a303458c5a26ad85b051 Mon Sep 17 00:00:00 2001 From: Harrison Liew Date: Sun, 6 Oct 2019 22:57:13 -0700 Subject: [PATCH 60/61] add ability to view gds using gdspy --- docs/VLSI/Tutorial.rst | 8 +++++ vlsi/view_gds.py | 66 ++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 74 insertions(+) create mode 100755 vlsi/view_gds.py diff --git a/docs/VLSI/Tutorial.rst b/docs/VLSI/Tutorial.rst index db1cee60..66a2f220 100644 --- a/docs/VLSI/Tutorial.rst +++ b/docs/VLSI/Tutorial.rst @@ -127,6 +127,14 @@ Intermediate database are written in ``build/par-rundir`` between each step of t Timing reports are found in ``build/par-rundir/timingReports``. They are gzipped text files. +`gdspy` can be used to `view the final layout `__, but it is somewhat crude and slow (wait a few minutes for it to load): + +.. code-block:: shell + + ``python3 view_gds.py build/par-rundir/Sha3AccelwBB.gds`` + +By default, this script only shows the M2 thru M4 routing. Layers can be toggled in the layout viewer's side pane and ``view_gds.py`` has a mapping of layer numbers to layer names. + DRC & LVS ^^^^^^^^^ To run DRC & LVS, and view the results in Calibre: diff --git a/vlsi/view_gds.py b/vlsi/view_gds.py new file mode 100755 index 00000000..edc94926 --- /dev/null +++ b/vlsi/view_gds.py @@ -0,0 +1,66 @@ +import sys + +try: + import gdspy +except ImportError: + print('Bad gdspy installation!') + sys.exit() + +print('Loading GDS...') +gds_lib = gdspy.GdsLibrary().read_gds(infile=str(sys.argv[1]), units='import') + +# Comment to show layer +hidden=[ + (1, 0), #well + (1, 251), #well lbl + (2, 0), #fin + (3, 0), #psub + (3, 251), #psub lbl + (7, 0), #gate + (8, 0), #dummy + (10, 0), #gate cut + (11, 0), #active + (12, 0), #nselect + (13, 0), #pselect + (16, 0), #LIG + (17, 0), #LISD + (18, 0), #V0 + (19, 0), #M1 + (19, 251), #M1 lbl + (21, 0), #V1 + #(20, 0), #M2 + (20, 251), #M2 lbl + #(25, 0), #V2 + #(30, 0), #M3 + (30, 251), #M3 lbl + #(35, 0), #V3 + #(40, 0), #M4 + (40, 251), #M4 lbl + (45, 0), #V4 + (50, 0), #M5 + (50, 251), #M5 lbl + (55, 0), #V5 + (60, 0), #M6 + (60, 251), #M6 lbl + (65, 0), #V6 + (70, 0), #M7 + (70, 251), #M7 lbl + (75, 0), #V7 + (80, 0), #M8 + (80, 251), #M8 lbl + (85, 0), #V8 + (88, 0), #SDT + (90, 0), #M9 + (90, 251), #M9 lbl + (95, 0), #V9 + (96, 0), #Pad + (97, 0), #SLVT + (98, 0), #LVT + (99, 0), #SRAMDRC + (100, 0), #??? + (101, 0), #??? + (110, 0) #SRAMVT + ] + +print('Opening layout...') +gdspy.LayoutViewer(gds_lib, hidden_types=hidden, depth=1) From 7df5ea68a861df198ae646004c0a5c98d13beaa7 Mon Sep 17 00:00:00 2001 From: David Biancolin Date: Mon, 7 Oct 2019 06:32:45 +0000 Subject: [PATCH 61/61] Bump FireSim for first batch of AGFIS [ci skip] --- sims/firesim | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/sims/firesim b/sims/firesim index 22ce787f..afd51ab7 160000 --- a/sims/firesim +++ b/sims/firesim @@ -1 +1 @@ -Subproject commit 22ce787fab2515c81bfbc98bbfdcd94b075d7a8a +Subproject commit afd51ab7a847ecb99593077db8d9e369c70242bd