Merge pull request #79 from ucb-bar/rebar_reorg

Decouple SUB_PROJECT builds from example

build.sbt

@@ -45,10 +45,13 @@ def conditionalDependsOn(prj: Project): Project = {
   }
 }
 
-lazy val example = conditionalDependsOn(project in file("."))
+lazy val example = conditionalDependsOn(project in file("example"))
   .dependsOn(boom, hwacha, sifive_blocks)
   .settings(commonSettings)
 
+lazy val utilities = conditionalDependsOn(project in file("utilities"))
+  .settings(commonSettings)
+
 lazy val hwacha = (project in file ("generators/hwacha"))
   .dependsOn(rebarrocketchip)
   .settings(commonSettings)

common.mk

@@ -8,8 +8,8 @@ SHELL=/bin/bash
 #########################################################################################
 lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null)
 
-PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks
-SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala)) $(call lookup_scala_srcs,$(base_dir)/src/main/scala)
+PACKAGES=rocket-chip testchipip boom hwacha sifive-blocks utilities example
+SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/generators/$(pkg)/src/main/scala))
 
 #########################################################################################
 # rocket and testchipip classes
@@ -32,7 +32,7 @@ $(FIRRTL_JAR): $(call lookup_scala_srcs, $(REBAR_FIRRTL_DIR)/src/main/scala)
 # create simulation args file rule
 #########################################################################################
 $(sim_dotf): $(SCALA_SOURCES) $(FIRRTL_JAR)
-	cd $(base_dir) && $(SBT) "runMain example.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
+	cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)"
 
 #########################################################################################
 # create firrtl file rule and variables

generators/example/src/main/scala/Configs.scala

@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32}
+import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize}
 import testchipip._
 
 // --------------
@@ -56,6 +56,10 @@ class GPIORocketConfig extends Config(
   new WithGPIORocketTop ++
   new BaseRocketConfig)
 
+class GB1MemoryConfig extends Config(
+  new WithExtMemSize((1<<30) * 1L) ++
+  new DefaultRocketConfig)
+
 // ------------
 // BOOM Configs
 // ------------

generators/utilities/src/main/scala/Simulator.scala

@@ -1,4 +1,4 @@
-package example
+package utilities
 
 import java.io.File
 
@@ -102,7 +102,7 @@ object GenerateSimFiles extends App with HasGenerateSimConfig {
     firrtl.FileUtils.makeDirectory("./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv64.img", "./bootrom/")
     writeResource("/testchipip/bootrom/bootrom.rv32.img", "./bootrom/")
-    writeResource("/project-template/bootrom/bootrom.img", "./bootrom/")
+    writeResource("/bootrom/bootrom.img", "./bootrom/")
   }
 
   def writeFiles(cfg: GenerateSimConfig): Unit = {