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bump rocket-chip for flattened coreplex/system

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This commit is contained in:
Howard Mao
2017-08-04 01:15:46 +00:00
parent cb79078641
commit 506afbb363
5 changed files with 16 additions and 21 deletions
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9
src/main/scala/example/PWM.scala
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@@ -2,8 +2,8 @@ package example
import chisel3._
import chisel3.util._
import freechips.rocketchip.coreplex.HasPeripheryBus
import freechips.rocketchip.config.{Parameters, Field}
import freechips.rocketchip.chip._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.regmapper.{HasRegMap, RegField}
import freechips.rocketchip.tilelink._
@@ -74,16 +74,15 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
new TLRegBundle(c, _) with PWMTLBundle)(
new TLRegModule(c, _, _) with PWMTLModule)
trait HasPeripheryPWM extends HasSystemNetworks {
trait HasPeripheryPWM extends HasPeripheryBus {
implicit val p: Parameters
private val address = 0x2000
val pwm = LazyModule(new PWMTL(
PWMParams(address, peripheryBusConfig.beatBytes))(p))
PWMParams(address, pbus.beatBytes))(p))
pwm.node := TLFragmenter(
peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
pwm.node := pbus.toVariableWidthSlaves
}
trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {