diff --git a/rocket-chip b/rocket-chip
index cf75c204..01ca3efc 160000
--- a/rocket-chip
+++ b/rocket-chip
@@ -1 +1 @@
-Subproject commit cf75c2049d0d1ebbed629fbd8a045acc669002d1
+Subproject commit 01ca3efc2be16a09156ea06018c10886dbfd7058
diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index 3c126268..10485db5 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -1,9 +1,8 @@
 package example
 
 import chisel3._
-import freechips.rocketchip.chip._
 import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.coreplex.WithRoccExample
+import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels}
 import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
@@ -34,7 +33,7 @@ class WithSimBlockDevice extends Config((site, here, up) => {
 })
 
 class BaseExampleConfig extends Config(
-  new freechips.rocketchip.chip.DefaultConfig)
+  new freechips.rocketchip.system.DefaultConfig)
 
 class DefaultExampleConfig extends Config(
   new WithExampleTop ++ new BaseExampleConfig)
diff --git a/src/main/scala/example/PWM.scala b/src/main/scala/example/PWM.scala
index 19294acb..1e501d2e 100644
--- a/src/main/scala/example/PWM.scala
+++ b/src/main/scala/example/PWM.scala
@@ -2,8 +2,8 @@ package example
 
 import chisel3._
 import chisel3.util._
+import freechips.rocketchip.coreplex.HasPeripheryBus
 import freechips.rocketchip.config.{Parameters, Field}
-import freechips.rocketchip.chip._
 import freechips.rocketchip.diplomacy._
 import freechips.rocketchip.regmapper.{HasRegMap, RegField}
 import freechips.rocketchip.tilelink._
@@ -74,16 +74,15 @@ class PWMTL(c: PWMParams)(implicit p: Parameters)
       new TLRegBundle(c, _) with PWMTLBundle)(
       new TLRegModule(c, _, _) with PWMTLModule)
 
-trait HasPeripheryPWM extends HasSystemNetworks {
+trait HasPeripheryPWM extends HasPeripheryBus {
   implicit val p: Parameters
 
   private val address = 0x2000
 
   val pwm = LazyModule(new PWMTL(
-    PWMParams(address, peripheryBusConfig.beatBytes))(p))
+    PWMParams(address, pbus.beatBytes))(p))
 
-  pwm.node := TLFragmenter(
-    peripheryBusConfig.beatBytes, cacheBlockBytes)(peripheryBus.node)
+  pwm.node := pbus.toVariableWidthSlaves
 }
 
 trait HasPeripheryPWMModuleImp extends LazyMultiIOModuleImp {
diff --git a/src/main/scala/example/Top.scala b/src/main/scala/example/Top.scala
index 16c148b7..5aa0a128 100644
--- a/src/main/scala/example/Top.scala
+++ b/src/main/scala/example/Top.scala
@@ -1,27 +1,24 @@
 package example
 
 import chisel3._
+import freechips.rocketchip.coreplex._
 import freechips.rocketchip.config.Parameters
-import freechips.rocketchip.chip._
+import freechips.rocketchip.devices.tilelink._
 import testchipip._
 
-class ExampleTop(implicit p: Parameters) extends BaseSystem
-    with HasPeripheryMasterAXI4MemPort
-    with HasPeripheryErrorSlave
-    with HasPeripheryZeroSlave
+class ExampleTop(implicit p: Parameters) extends RocketCoreplex
+    with HasMasterAXI4MemPort
     with HasPeripheryBootROM
-    with HasPeripheryRTCCounter
-    with HasRocketPlexMaster
+    with HasPeripheryErrorSlave
     with HasNoDebug
     with HasPeripherySerial {
   override lazy val module = new ExampleTopModule(this)
 }
 
-class ExampleTopModule[+L <: ExampleTop](l: L) extends BaseSystemModule(l)
-    with HasPeripheryMasterAXI4MemPortModuleImp
+class ExampleTopModule[+L <: ExampleTop](l: L) extends RocketCoreplexModule(l)
+    with HasRTCModuleImp
+    with HasMasterAXI4MemPortModuleImp
     with HasPeripheryBootROMModuleImp
-    with HasPeripheryRTCCounterModuleImp
-    with HasRocketPlexMasterModuleImp
     with HasNoDebugModuleImp
     with HasPeripherySerialModuleImp
 
diff --git a/testchipip b/testchipip
index fa3dd9ab..d1fe6434 160000
--- a/testchipip
+++ b/testchipip
@@ -1 +1 @@
-Subproject commit fa3dd9ab0844f8d23c76d1fd0abc28c671b1d06a
+Subproject commit d1fe6434d7b8df206c936ee79cbe2465672cbd6f