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Enable debug SBA on all default designs

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This commit is contained in:
Jerry Zhao
2024-01-25 16:30:46 -08:00
committed by GitHub
parent 150f888a62
commit 4f3dd60670
1 changed files with 1 additions and 0 deletions
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generators/chipyard/src/main/scala/config/AbstractConfig.scala
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@@ -83,6 +83,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
new freechips.rocketchip.subsystem.WithDebugSBA ++ // enable the SBA (system-bus-access) feature of the debug module
new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)