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commenting out the sram macro placement FOR NOW

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Nayiri K
2022-09-14 17:51:57 -07:00
parent 5c48d039a0
commit 4ee1acc522
1 changed files with 88 additions and 85 deletions
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173
vlsi/example-sky130.yml
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@@ -6,9 +6,12 @@ vlsi.core.max_threads: 12
# Technology paths # Technology paths
technology.sky130: technology.sky130:
sky130A: "path-to-sky130A/" # sky130A: "path-to-sky130A/"
sky130_nda: "path-to-skywater-src-nda/" sky130_nda: "path-to-skywater-src-nda/"
openram_lib: "path-to-sky130_sram_macros/" # openram_lib: "path-to-sky130_sram_macros/"
sky130A: "/tools/C/nayiri/sky130/sky130A"
# sky130_nda: "path-to-skywater-src-nda/"
openram_lib: "/tools/C/nayiri/sky130/sky130_sram_macros"
# General Hammer Inputs # General Hammer Inputs
@@ -62,105 +65,105 @@ vlsi.inputs.placement_constraints:
top: 0 top: 0
bottom: 0 bottom: 0
# Place data cache SRAM instances # # Place data cache SRAM instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro # type: hardmacro
x: 50 # x: 50
y: 100 # y: 100
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro # type: hardmacro
x: 50 # x: 50
y: 700 # y: 700
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
type: hardmacro # type: hardmacro
x: 50 # x: 50
y: 1300 # y: 1300
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
type: hardmacro # type: hardmacro
x: 50 # x: 50
y: 1900 # y: 1900
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
type: hardmacro # type: hardmacro
x: 1000 # x: 1000
y: 1900 # y: 1900
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
type: hardmacro # type: hardmacro
x: 1000 # x: 1000
y: 1300 # y: 1300
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
type: hardmacro # type: hardmacro
x: 1000 # x: 1000
y: 700 # y: 700
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
type: hardmacro # type: hardmacro
x: 1000 # x: 1000
y: 100 # y: 100
orientation: r0 # orientation: r0
# Place instruction cache SRAM instances # # Place instruction cache SRAM instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro # type: hardmacro
x: 3700 # x: 3700
y: 100 # y: 100
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
type: hardmacro # type: hardmacro
x: 3700 # x: 3700
y: 700 # y: 700
orientation: r0 # orientation: r0
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
type: hardmacro # type: hardmacro
x: 3000 # x: 3000
y: 100 # y: 100
orientation: r0 # orientation: r0
# Place L2 TLB SRAM instances # # Place L2 TLB SRAM instances
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
type: hardmacro # type: hardmacro
x: 1900 # x: 1900
y: 1900 # y: 1900
orientation: "r0" # orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
type: hardmacro # type: hardmacro
x: 2600 # x: 2600
y: 1900 # y: 1900
orientation: "r0" # orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
type: hardmacro # type: hardmacro
x: 3300 # x: 3300
y: 1900 # y: 1900
orientation: "r0" # orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
type: hardmacro # type: hardmacro
x: 3950 # x: 3950
y: 1900 # y: 1900
orientation: "r0" # orientation: "r0"
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4" # - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
type: hardmacro # type: hardmacro
x: 3950 # x: 3950
y: 1300 # y: 1300
orientation: "r0" # orientation: "r0"
# Pin placement constraints # Pin placement constraints
vlsi.inputs.pin_mode: generated vlsi.inputs.pin_mode: generated