180 lines
5.1 KiB
YAML
180 lines
5.1 KiB
YAML
# Technology Setup
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# Technology used is Sky130
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vlsi.core.technology: sky130
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vlsi.core.max_threads: 12
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# Technology paths
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technology.sky130:
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# sky130A: "path-to-sky130A/"
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sky130_nda: "path-to-skywater-src-nda/"
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# openram_lib: "path-to-sky130_sram_macros/"
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sky130A: "/tools/C/nayiri/sky130/sky130A"
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# sky130_nda: "path-to-skywater-src-nda/"
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openram_lib: "/tools/C/nayiri/sky130/sky130_sram_macros"
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# General Hammer Inputs
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# Hammer will auto-generate a CPF for simple power designs; see hammer/src/hammer-vlsi/defaults.yml for more info
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vlsi.inputs.power_spec_mode: "auto"
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vlsi.inputs.power_spec_type: "cpf"
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# Specify clock signals
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vlsi.inputs.clocks: [
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{name: "clock_clock", period: "10ns", uncertainty: "1ns"}
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]
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# Generate Make include to aid in flow
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vlsi.core.build_system: make
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# Power Straps
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par.power_straps_mode: generate
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par.generate_power_straps_method: by_tracks
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par.blockage_spacing: 40.0
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par.blockage_spacing_top_layer: met4
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par.generate_power_straps_options:
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by_tracks:
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strap_layers:
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- met4
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- met5
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pin_layers:
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- met5
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blockage_spacing_met2: 4.0
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blockage_spacing_met4: 2.0
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blockage_spacing_met4: 2.0
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track_width: 3
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track_width_met5: 1
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track_spacing: 5
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track_start: 10
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track_start_met5: 1
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power_utilization: 0.1
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power_utilization_met4: 0.1
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power_utilization_met5: 0.1
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# Placement Constraints
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vlsi.inputs.placement_constraints:
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- path: "ChipTop"
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type: toplevel
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x: 0
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y: 0
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width: 3800
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height: 2500
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margins:
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left: 0
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right: 0
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top: 0
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bottom: 0
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# # Place data cache SRAM instances
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
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# type: hardmacro
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# x: 50
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# y: 100
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
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# type: hardmacro
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# x: 50
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_2_0"
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# type: hardmacro
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# x: 50
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# y: 1300
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_3_0"
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# type: hardmacro
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# x: 50
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# y: 1900
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_4_0"
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# type: hardmacro
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# x: 1000
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# y: 1900
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_5_0"
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# type: hardmacro
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# x: 1000
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# y: 1300
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_6_0"
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# type: hardmacro
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# x: 1000
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_7_0"
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# type: hardmacro
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# x: 1000
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# y: 100
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# orientation: r0
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# # Place instruction cache SRAM instances
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_0_0"
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# type: hardmacro
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# x: 3700
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# y: 100
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/data_arrays_0/data_arrays_0_0_ext/mem_1_0"
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# type: hardmacro
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# x: 3700
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# y: 700
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# orientation: r0
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/frontend/icache/tag_array/tag_array_ext/mem_0_0"
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# type: hardmacro
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# x: 3000
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# y: 100
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# orientation: r0
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# # Place L2 TLB SRAM instances
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_0"
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# type: hardmacro
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# x: 1900
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_1"
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# type: hardmacro
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# x: 2600
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_2"
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# type: hardmacro
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# x: 3300
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_3"
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# type: hardmacro
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# x: 3950
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# y: 1900
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# orientation: "r0"
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# - path: "ChipTop/system/tile_prci_domain/tile_reset_domain/tile/ptw/l2_tlb_ram/l2_tlb_ram_ext/mem_0_4"
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# type: hardmacro
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# x: 3950
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# y: 1300
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# orientation: "r0"
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# Pin placement constraints
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vlsi.inputs.pin_mode: generated
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vlsi.inputs.pin.generate_mode: semi_auto
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vlsi.inputs.pin.assignments: [
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{pins: "*", layers: ["met2", "met4"], side: "bottom"}
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]
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# SRAM Compiler compiler options
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vlsi.core.sram_generator_tool: "sram_compiler"
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# You should specify a location for the SRAM generator in the tech plugin
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vlsi.core.sram_generator_tool_path: ["hammer/src/hammer-vlsi/technology/sky130"]
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vlsi.core.sram_generator_tool_path_meta: "append"
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