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have core 0 interrupt other cores

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Howard Mao
2017-09-12 20:33:36 -07:00
parent 2a4e994b09
commit 4dd2d5f881
4 changed files with 22 additions and 4 deletions
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6
src/main/scala/example/Configs.scala
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@@ -2,7 +2,7 @@ package example
import chisel3._
import freechips.rocketchip.config.{Parameters, Config}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels}
import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores}
import freechips.rocketchip.diplomacy.LazyModule
import testchipip._
@@ -54,3 +54,7 @@ class WithFourTrackers extends WithNBlockDeviceTrackers(4)
class WithTwoMemChannels extends WithNMemoryChannels(2)
class WithFourMemChannels extends WithNMemoryChannels(4)
class DualCoreConfig extends Config(
// Core gets tacked onto existing list
new WithNBigCores(1) ++ new DefaultExampleConfig)