From 4dd2d5f881a953ccd274c8e81dfe2f657baa6fa9 Mon Sep 17 00:00:00 2001
From: Howard Mao <zhehao.mao@gmail.com>
Date: Tue, 12 Sep 2017 20:33:36 -0700
Subject: [PATCH] have core 0 interrupt other cores

---
 bootrom/Makefile                     |   5 ++++-
 bootrom/bootrom.S                    |  15 +++++++++++++--
 bootrom/bootrom.img                  | Bin 96 -> 96 bytes
 src/main/scala/example/Configs.scala |   6 +++++-
 4 files changed, 22 insertions(+), 4 deletions(-)

diff --git a/bootrom/Makefile b/bootrom/Makefile
index 2a487dac..fd214590 100644
--- a/bootrom/Makefile
+++ b/bootrom/Makefile
@@ -1,10 +1,13 @@
 bootrom_img = bootrom.img
+bootrom_dump = bootrom.dump
 
 GCC=riscv64-unknown-elf-gcc
 OBJCOPY=riscv64-unknown-elf-objcopy
 OBJDUMP=riscv64-unknown-elf-objdump
 
-all: $(bootrom_img)
+img: $(bootrom_img)
+
+dump: $(bootrom_dump)
 
 %.img: %.elf
 	$(OBJCOPY) -O binary --change-addresses=-0x10000 $< $@
diff --git a/bootrom/bootrom.S b/bootrom/bootrom.S
index 6b2e973a..e6cf0fa7 100644
--- a/bootrom/bootrom.S
+++ b/bootrom/bootrom.S
@@ -3,9 +3,20 @@
 .section .text.start, "ax", @progbits
 .globl _start
 _start:
-  csrr a0, mhartid
-  sll a0, a0, 2 // offset for hart msip
   li a1, 0x2000000 // base address of clint
+  csrr a0, mhartid
+  bnez a0, boot_core
+
+  addi a2, a1, 4
+  li a3, 1
+interrupt_loop:
+  sw a3, 0(a2)
+  addi a2, a2, 4
+  lw a3, -4(a2)
+  bnez a3, interrupt_loop
+
+boot_core:
+  sll a0, a0, 2 // offset for hart msip
   add a0, a0, a1
   sw zero, 0(a0) // clear the interrupt
   li a0, DRAM_BASE // program reset vector
diff --git a/bootrom/bootrom.img b/bootrom/bootrom.img
index 040dc666e7b2323b84f57eb18dc12e0a4aa57049..b2e4bf2c506a3eec5635478e28dec434e856c720 100755
GIT binary patch
delta 44
zcmYdDklD`4z*Ma2@R9SSaGNVbtDDFnLAGYKWB;H2<6@o2CBycVshB~*V4|H808Cg8
AqyPW_

delta 44
kcmYdD;3`&i_{hb&ot1%UqKu3LD@!qhf&l{tm}sX20JK~M{{R30

diff --git a/src/main/scala/example/Configs.scala b/src/main/scala/example/Configs.scala
index 10485db5..f02dc6e9 100644
--- a/src/main/scala/example/Configs.scala
+++ b/src/main/scala/example/Configs.scala
@@ -2,7 +2,7 @@ package example
 
 import chisel3._
 import freechips.rocketchip.config.{Parameters, Config}
-import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels}
+import freechips.rocketchip.coreplex.{WithRoccExample, WithNMemoryChannels, WithNBigCores}
 import freechips.rocketchip.diplomacy.LazyModule
 import testchipip._
 
@@ -54,3 +54,7 @@ class WithFourTrackers extends WithNBlockDeviceTrackers(4)
 
 class WithTwoMemChannels extends WithNMemoryChannels(2)
 class WithFourMemChannels extends WithNMemoryChannels(4)
+
+class DualCoreConfig extends Config(
+  // Core gets tacked onto existing list
+  new WithNBigCores(1) ++ new DefaultExampleConfig)