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Bump testchipip

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abejgonzalez
2021-01-04 15:36:00 -08:00
parent c8cbfbe3c5
commit 4d3ff26a73
3 changed files with 13 additions and 7 deletions
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12
fpga/src/main/scala/vcu118/bringup/Configs.scala
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@@ -6,6 +6,7 @@ import freechips.rocketchip.config.{Config, Parameters}
import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress} import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
import freechips.rocketchip.tilelink._ import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem.{MasterPortParams}
import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams} import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams} import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
@@ -39,10 +40,9 @@ class WithBringupPeripherals extends Config((site, here, up) => {
case TSIClockMaxFrequencyKey => 100 case TSIClockMaxFrequencyKey => 100
case PeripheryTSIHostKey => List( case PeripheryTSIHostKey => List(
TSIHostParams( TSIHostParams(
serialIfWidth = 4, offchipSerialIfWidth = 4,
mmioBaseAddress = BigInt(0x64006000), mmioBaseAddress = BigInt(0x64006000),
mmioSourceId = 1 << 13, // manager source mmioSourceId = 1 << 13, // manager source
targetSize = site(VCU118DDR2Size),
serdesParams = TSIHostSerdesParams( serdesParams = TSIHostSerdesParams(
clientPortParams = TLMasterPortParameters.v1( clientPortParams = TLMasterPortParameters.v1(
clients = Seq(TLMasterParameters.v1( clients = Seq(TLMasterParameters.v1(
@@ -61,7 +61,13 @@ class WithBringupPeripherals extends Config((site, here, up) => {
supportsArithmetic = TransferSizes(1, 64), supportsArithmetic = TransferSizes(1, 64),
supportsLogical = TransferSizes(1, 64))), supportsLogical = TransferSizes(1, 64))),
endSinkId = 1 << 6, // manager sink endSinkId = 1 << 6, // manager sink
beatBytes = 8)))) beatBytes = 8)),
targetMasterPortParams = MasterPortParams(
base = BigInt("80000000", 16),
size = site(VCU118DDR2Size),
beatBytes = 8, // comes from test chip
idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG
))
}) })
class WithBringupVCU118System extends Config((site, here, up) => { class WithBringupVCU118System extends Config((site, here, up) => {

6
fpga/src/main/scala/vcu118/bringup/TestHarness.scala
View File

@@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput())) val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth))) val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth)))
dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb)) dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
// connect 1 mem. channel to the FPGA DDR // connect 1 mem. channel to the FPGA DDR
val inTsiParams = topDesign match { case td: ChipTop => val inTsiParams = topDesign match { case td: ChipTop =>

2
generators/testchipip

Submodule generators/testchipip updated: 0e06d3c054...39ed56be3e