diff --git a/fpga/src/main/scala/vcu118/bringup/Configs.scala b/fpga/src/main/scala/vcu118/bringup/Configs.scala
index ec1ea1e3..62c2af31 100644
--- a/fpga/src/main/scala/vcu118/bringup/Configs.scala
+++ b/fpga/src/main/scala/vcu118/bringup/Configs.scala
@@ -6,6 +6,7 @@ import freechips.rocketchip.config.{Config, Parameters}
 import freechips.rocketchip.diplomacy.{DTSModel, DTSTimebase, RegionType, AddressSet, ResourceBinding, Resource, ResourceAddress}
 import freechips.rocketchip.tilelink._
 import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.subsystem.{MasterPortParams}
 
 import sifive.blocks.devices.gpio.{PeripheryGPIOKey, GPIOParams}
 import sifive.blocks.devices.i2c.{PeripheryI2CKey, I2CParams}
@@ -39,10 +40,9 @@ class WithBringupPeripherals extends Config((site, here, up) => {
   case TSIClockMaxFrequencyKey => 100
   case PeripheryTSIHostKey => List(
     TSIHostParams(
-      serialIfWidth = 4,
+      offchipSerialIfWidth = 4,
       mmioBaseAddress = BigInt(0x64006000),
       mmioSourceId = 1 << 13, // manager source
-      targetSize = site(VCU118DDR2Size),
       serdesParams = TSIHostSerdesParams(
         clientPortParams = TLMasterPortParameters.v1(
           clients = Seq(TLMasterParameters.v1(
@@ -61,7 +61,13 @@ class WithBringupPeripherals extends Config((site, here, up) => {
             supportsArithmetic = TransferSizes(1, 64),
             supportsLogical    = TransferSizes(1, 64))),
           endSinkId = 1 << 6, // manager sink
-          beatBytes = 8))))
+          beatBytes = 8)),
+      targetMasterPortParams = MasterPortParams(
+        base = BigInt("80000000", 16),
+        size = site(VCU118DDR2Size),
+        beatBytes = 8, // comes from test chip
+        idBits = 4) // comes from VCU118 idBits in XilinxVCU118MIG
+      ))
 })
 
 class WithBringupVCU118System extends Config((site, here, up) => {
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 2e86e646..2406cb7b 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -72,10 +72,10 @@ class BringupVCU118FPGATestHarness(override implicit val p: Parameters) extends
 
   val tsi_host = Overlay(TSIHostOverlayKey, new BringupTSIHostVCU118ShellPlacer(this, TSIHostShellInput()))
 
-  val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetBaseAddress, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
+  val ddr2Node = dp(DDROverlayKey).last.place(DDRDesignInput(dp(PeripheryTSIHostKey).head.targetMasterPortParams.base, ddr2Wrangler.node, ddr2PLL)).overlayOutput.ddr
 
-  val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.serialIfWidth)))
-  dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.serialIfWidth, io_tsi_serial_bb))
+  val io_tsi_serial_bb = BundleBridgeSource(() => (new TSIHostWidgetIO(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth)))
+  dp(TSIHostOverlayKey).head.place(TSIHostDesignInput(dp(PeripheryTSIHostKey).head.offchipSerialIfWidth, io_tsi_serial_bb))
 
   // connect 1 mem. channel to the FPGA DDR
   val inTsiParams = topDesign match { case td: ChipTop =>
diff --git a/generators/testchipip b/generators/testchipip
index 0e06d3c0..39ed56be 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 0e06d3c054ddbc9c3d3fc7681819b52b1d1f40fd
+Subproject commit 39ed56be3e72ce09f64889b9d63c8b9fd98eb726