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Small spacing fixes

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abejgonzalez
2021-03-18 20:01:45 -07:00
parent 7b7bcf7996
commit 4a565088b5
1 changed files with 1 additions and 1 deletions
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2
generators/chipyard/src/main/scala/TestHarness.scala
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@@ -43,7 +43,7 @@ class HarnessClockInstantiator {
// connect all clock wires specified to a divider only PLL
def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = {
val sinks = _clockMap.map({ case (name, (freq, bundle)) =>
ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq/1000000)),name=Some(name))
ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name))
}).toSeq
val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks)