From 4a565088b51265230049bc0ea6869d00e1d596ad Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Thu, 18 Mar 2021 20:01:45 -0700 Subject: [PATCH] Small spacing fixes --- generators/chipyard/src/main/scala/TestHarness.scala | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/TestHarness.scala b/generators/chipyard/src/main/scala/TestHarness.scala index 82be0093..d8c7ec20 100644 --- a/generators/chipyard/src/main/scala/TestHarness.scala +++ b/generators/chipyard/src/main/scala/TestHarness.scala @@ -43,7 +43,7 @@ class HarnessClockInstantiator { // connect all clock wires specified to a divider only PLL def instantiateHarnessDividerPLL(refClock: ClockBundle): Unit = { val sinks = _clockMap.map({ case (name, (freq, bundle)) => - ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq/1000000)),name=Some(name)) + ClockSinkParameters(take=Some(ClockParameters(freqMHz=freq / (1000 * 1000))), name=Some(name)) }).toSeq val pllConfig = new SimplePllConfiguration("harnessDividerOnlyClockGenerator", sinks)