Merge pull request #128 from ucb-bar/dev-L2

Add SiFive InclusiveCache

generators/example/src/main/scala/Configs.scala

@@ -3,7 +3,7 @@ package example
 import chisel3._
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks}
+import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
 
 import testchipip._
 
@@ -62,6 +62,9 @@ class GB1MemoryConfig extends Config(
   new WithExtMemSize((1<<30) * 1L) ++
   new DefaultRocketConfig)
 
+class RocketL2Config extends Config(
+  new WithInclusiveCache ++ new DefaultRocketConfig)
+
 // ------------
 // BOOM Configs
 // ------------
@@ -142,6 +145,9 @@ class RV32UnifiedBoomConfig extends Config(
   new WithBootROM ++
   new boom.system.SmallRV32UnifiedBoomConfig)
 
+class BoomL2Config extends Config(
+  new WithInclusiveCache ++ new SmallDefaultBoomConfig)
+
 // ---------------------
 // BOOM and Rocket Configs
 // ---------------------
@@ -247,3 +253,6 @@ class RV32BoomAndRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithRV32 ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
+
+class DualCoreRocketL2Config extends Config(
+  new WithInclusiveCache ++ new DualCoreRocketConfig)