Merge pull request #128 from ucb-bar/dev-L2

Add SiFive InclusiveCache

.gitmodules

@@ -37,3 +37,6 @@
 [submodule "generators/icenet"]
 	path = generators/icenet
 	url = https://github.com/firesim/icenet.git
+[submodule "generators/block-inclusivecache-sifive"]
+	path = generators/sifive-cache
+	url = https://github.com/sifive/block-inclusivecache-sifive.git

build.sbt

@@ -81,7 +81,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
   .settings(commonSettings)
 
 lazy val example = conditionalDependsOn(project in file("generators/example"))
-  .dependsOn(boom, hwacha, sifive_blocks)
+  .dependsOn(boom, hwacha, sifive_blocks, sifive_cache)
   .settings(commonSettings)
 
 lazy val utilities = conditionalDependsOn(project in file("generators/utilities"))
@@ -114,12 +114,17 @@ lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
+lazy val sifive_cache = (project in file("generators/sifive-cache")).settings(
+    commonSettings,
+    scalaSource in Compile := baseDirectory.value / "craft"
+  ).dependsOn(rocketchip)
+
 // Library components of FireSim
 lazy val midas      = ProjectRef(firesimDir, "midas")
 lazy val firesimLib = ProjectRef(firesimDir, "firesimLib")
 
 lazy val firechip = (project in file("generators/firechip"))
-  .dependsOn(boom, icenet, testchipip, sifive_blocks, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
+  .dependsOn(boom, icenet, testchipip, sifive_blocks, sifive_cache, midasTargetUtils, midas, firesimLib % "test->test;compile->compile")
   .settings(
     commonSettings,
     testGrouping in Test := isolateAllTests( (definedTests in Test).value )

common.mk

@@ -8,7 +8,7 @@ SHELL=/bin/bash
 #########################################################################################
 lookup_scala_srcs = $(shell find -L $(1)/ -iname "*.scala" 2> /dev/null)
 
-PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks example) \
+PACKAGES=$(addprefix generators/, rocket-chip testchipip boom hwacha sifive-blocks sifive-cache example) \
 		 $(addprefix sims/firesim/sim/, . firesim-lib midas midas/targetutils)
 SCALA_SOURCES=$(foreach pkg,$(PACKAGES),$(call lookup_scala_srcs,$(base_dir)/$(pkg)/src/main/scala))
 

generators/example/src/main/scala/Configs.scala

@@ -3,7 +3,7 @@ package example
 import chisel3._
 
 import freechips.rocketchip.config.{Config}
-import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks}
+import freechips.rocketchip.subsystem.{WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, WithExtMemSize, WithNBanks, WithInclusiveCache}
 
 import testchipip._
 
@@ -62,6 +62,9 @@ class GB1MemoryConfig extends Config(
   new WithExtMemSize((1<<30) * 1L) ++
   new DefaultRocketConfig)
 
+class RocketL2Config extends Config(
+  new WithInclusiveCache ++ new DefaultRocketConfig)
+
 // ------------
 // BOOM Configs
 // ------------
@@ -142,6 +145,9 @@ class RV32UnifiedBoomConfig extends Config(
   new WithBootROM ++
   new boom.system.SmallRV32UnifiedBoomConfig)
 
+class BoomL2Config extends Config(
+  new WithInclusiveCache ++ new SmallDefaultBoomConfig)
+
 // ---------------------
 // BOOM and Rocket Configs
 // ---------------------
@@ -247,3 +253,6 @@ class RV32BoomAndRocketConfig extends Config(
   new freechips.rocketchip.subsystem.WithRV32 ++
   new freechips.rocketchip.subsystem.WithNBigCores(1) ++
   new freechips.rocketchip.system.BaseConfig)
+
+class DualCoreRocketL2Config extends Config(
+  new WithInclusiveCache ++ new DualCoreRocketConfig)