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Support banked/partitioned scratchpads

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This commit is contained in:
Jerry Zhao
2023-04-08 16:38:36 -07:00
parent 32a19a793d
commit 471f8879d7
3 changed files with 11 additions and 5 deletions
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2
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -16,7 +16,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHavePeripheryCustomBootPin // Enables optional custom boot pin
with testchipip.CanHavePeripheryBootAddrReg // Use programmable boot address register
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHaveBankedScratchpad // Enables optionally adding a banked scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
with testchipip.CanHavePeripheryTLSerial // Enables optionally adding the backing memory and serial adapter
with sifive.blocks.devices.i2c.HasPeripheryI2C // Enables optionally adding the sifive I2C

12
generators/chipyard/src/main/scala/config/RocketConfigs.scala
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@@ -74,13 +74,19 @@ class L1ScratchpadRocketConfig extends Config(
new chipyard.config.AbstractConfig)
// DOC include start: mbusscratchpadrocket
class MbusScratchpadRocketConfig extends Config(
new testchipip.WithBackingScratchpad ++ // add mbus backing scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
class MbusScratchpadOnlyRocketConfig extends Config(
new testchipip.WithMbusScratchpad(stripes=2, partitions=2) ++ // add 4 banks mbus backing scratchpad
new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
// DOC include end: mbusscratchpadrocket
class SbusScratchpadRocketConfig extends Config(
new testchipip.WithSbusScratchpad(base=0x70000000L, stripes=2, partitions=2) ++ // add 4 lanes sbus backing scratchpad
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new chipyard.config.AbstractConfig)
class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithAsynchronousRocketTiles(3, 3) ++ // Add async crossings between RocketTile and uncore
new freechips.rocketchip.subsystem.WithNBigCores(1) ++

2
generators/testchipip

Submodule generators/testchipip updated: a3e9c1ffea...8a1540ce90