wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Merge remote-tracking branch 'origin/main' into symmetric_sertl

Browse Source
This commit is contained in:
Jerry Zhao
2024-01-11 11:43:24 -08:00
parent 96ffc8f0a1 8073ecb1e8
commit 45d74f6db2
84 changed files with 411 additions and 271 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
generators/firechip/src/main/scala/FireSim.scala
View File

@@ -8,7 +8,7 @@ import chisel3._
import chisel3.experimental.{IO, annotate}
import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, HasTiles}
import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
@@ -103,8 +103,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
// FireSim ModelMultithreading
chiptops.foreach {
case c: ChipTop => c.lazySystem match {
case ls: HasTiles => {
if (p(FireSimMultiCycleRegFile)) ls.tiles.map {
case ls: InstantiatesHierarchicalElements => {
if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
@@ -120,7 +120,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
}
case _ =>
}
if (p(FireSimFAME5)) ls.tiles.map {
if (p(FireSimFAME5)) ls.totalTiles.values.map {
case b: BoomTile =>
annotate(EnableModelMultiThreadingAnnotation(b.module))
case r: RocketTile =>

5
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -85,6 +85,7 @@ class WithMinimalFireSimDesignTweaks extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
new chipyard.harness.WithClockFromHarness ++
new chipyard.harness.WithResetFromHarness ++
new chipyard.config.WithNoClockTap ++
new chipyard.clocking.WithPassthroughClockGenerator ++
// Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
new WithBootROM ++
@@ -99,6 +100,8 @@ class WithMinimalFireSimDesignTweaks extends Config(
// Non-frequency tweaks that are generally applied to all firesim configs
class WithFireSimDesignTweaks extends Config(
new WithMinimalFireSimDesignTweaks ++
// Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
new chipyard.config.WithNoClockTap ++
// Required: Bake in the default FASED memory model
new WithDefaultMemModel ++
// Optional: reduce the width of the Serial TL interface
@@ -122,6 +125,7 @@ class WithFireSimHighPerfClocking extends Config(
// This frequency selection matches FireSim's legacy selection and is required
// to support 200Gb NIC performance. You may select a smaller value.
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
new chipyard.config.WithControlBusFrequency(3200.0) ++
new chipyard.config.WithSystemBusFrequency(3200.0) ++
new chipyard.config.WithFrontBusFrequency(3200.0) ++
new chipyard.config.WithControlBusFrequency(3200.0) ++
@@ -142,6 +146,7 @@ class WithFireSimConfigTweaks extends Config(
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithFrontBusFrequency(1000.0) ++
new WithFireSimDesignTweaks