diff --git a/.github/actions/create-conda-env/action.yml b/.github/actions/create-conda-env/action.yml
index e29a06e9..b9fd6066 100644
--- a/.github/actions/create-conda-env/action.yml
+++ b/.github/actions/create-conda-env/action.yml
@@ -11,7 +11,6 @@ runs:
echo "Creating a conda environment for each toolchain with the toolchain installed"
conda activate base
conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-riscv-tools ./conda-reqs/conda-lock-reqs/conda-requirements-riscv-tools-linux-64.conda-lock.yml
- conda-lock install --conda $(which conda) -n ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools ./conda-reqs/conda-lock-reqs/conda-requirements-esp-tools-linux-64.conda-lock.yml
conda deactivate
echo "Add extra toolchain collateral + CIRCT to RISC-V install area"
@@ -25,14 +24,5 @@ runs:
-x ./conda-reqs/circt.json \
-g ${{ github.token }}
conda deactivate
- conda activate ${{ env.conda-env-name-no-time }}-$(date --date "${{ env.workflow-timestamp }}" +%Y%m%d)-esp-tools
- ./scripts/build-toolchain-extra.sh esp-tools -p $CONDA_PREFIX/esp-tools
- ./tools/install-circt/bin/download-release-or-nightly-circt.sh \
- -f circt-full-shared-linux-x64.tar.gz \
- -i $CONDA_PREFIX \
- -v version-file \
- -x ./conda-reqs/circt.json \
- -g ${{ github.token }}
- conda deactivate
fi
shell: bash -leo pipefail {0}
diff --git a/.github/scripts/check-commit.sh b/.github/scripts/check-commit.sh
index d3b856c8..a4a95611 100755
--- a/.github/scripts/check-commit.sh
+++ b/.github/scripts/check-commit.sh
@@ -45,7 +45,7 @@ search () {
done
}
-submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
+submodules=("cva6" "boom" "ibex" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "rocket-chip-blocks" "rocket-chip-inclusive-cache" "testchipip" "riscv-sodor" "mempress" "bar-fetchers" "shuttle" "constellation" "fft-generator" "hardfloat" "caliptra-aes-acc" "rocc-acc-utils")
dir="generators"
branches=("master" "main" "dev")
search
diff --git a/.github/scripts/defaults.sh b/.github/scripts/defaults.sh
index 94339a5b..ef7453d2 100755
--- a/.github/scripts/defaults.sh
+++ b/.github/scripts/defaults.sh
@@ -33,7 +33,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-dmiboom chipyard-spif
grouping["group-accels"]="chipyard-mempress chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-manymmioaccels chipyard-nvdla chipyard-aes256ecb"
grouping["group-constellation"]="chipyard-constellation"
grouping["group-tracegen"]="tracegen tracegen-boom"
-grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar"
+grouping["group-other"]="icenet testchipip constellation rocketchip-amba rocketchip-tlsimple rocketchip-tlwidth rocketchip-tlxbar chipyard-clusters"
grouping["group-fpga"]="arty35t arty100t nexysvideo vc707 vcu118"
# key value store to get the build strings
@@ -68,6 +68,7 @@ mapping["chipyard-shuttle"]=" CONFIG=ShuttleConfig"
mapping["chipyard-multiclock-rocket"]=" CONFIG=MulticlockRocketConfig"
mapping["chipyard-nomem-scratchpad"]=" CONFIG=MMIOScratchpadOnlyRocketConfig"
mapping["chipyard-constellation"]=" CONFIG=SharedNoCConfig"
+mapping["chipyard-clusters"]=" CONFIG=ClusteredRocketConfig verilog"
mapping["chipyard-aes256ecb"]=" CONFIG=AES256ECBRocketConfig"
mapping["constellation"]=" SUB_PROJECT=constellation"
diff --git a/.gitmodules b/.gitmodules
index e1768873..86f29d8a 100644
--- a/.gitmodules
+++ b/.gitmodules
@@ -13,9 +13,6 @@
[submodule "generators/boom"]
path = generators/boom
url = https://github.com/riscv-boom/riscv-boom.git
-[submodule "generators/sifive-blocks"]
- path = generators/sifive-blocks
- url = https://github.com/chipsalliance/rocket-chip-blocks.git
[submodule "generators/hwacha"]
path = generators/hwacha
url = https://github.com/ucb-bar/hwacha.git
@@ -25,9 +22,6 @@
[submodule "generators/icenet"]
path = generators/icenet
url = https://github.com/firesim/icenet.git
-[submodule "generators/block-inclusivecache-sifive"]
- path = generators/sifive-cache
- url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
[submodule "tools/dsptools"]
path = tools/dsptools
url = https://github.com/ucb-bar/dsptools.git
@@ -64,6 +58,9 @@
[submodule "software/nvdla-workload"]
path = software/nvdla-workload
url = https://github.com/ucb-bar/nvdla-workload.git
+[submodule "software/baremetal-ide"]
+ path = software/baremetal-ide
+ url = https://github.com/ucb-bar/Baremetal-IDE.git
[submodule "generators/riscv-sodor"]
path = generators/riscv-sodor
url = https://github.com/ucb-bar/riscv-sodor.git
@@ -145,3 +142,9 @@
[submodule "toolchains/riscv-tools/riscv-spike-devices"]
path = toolchains/riscv-tools/riscv-spike-devices
url = https://github.com/ucb-bar/spike-devices.git
+[submodule "generators/rocket-chip-blocks"]
+ path = generators/rocket-chip-blocks
+ url = https://github.com/chipsalliance/rocket-chip-blocks.git
+[submodule "generators/rocket-chip-inclusive-cache"]
+ path = generators/rocket-chip-inclusive-cache
+ url = https://github.com/chipsalliance/rocket-chip-inclusive-cache.git
diff --git a/build.sbt b/build.sbt
index c3be6161..2288cded 100644
--- a/build.sbt
+++ b/build.sbt
@@ -95,7 +95,7 @@ lazy val chiselSettings = Seq(
// -- Rocket Chip --
-lazy val hardfloat = freshProject("hardfloat", rocketChipDir / "hardfloat/hardfloat")
+lazy val hardfloat = freshProject("hardfloat", file("generators/hardfloat/hardfloat"))
.settings(chiselSettings)
.dependsOn(midasTargetUtils)
.settings(commonSettings)
@@ -141,12 +141,12 @@ lazy val rocketLibDeps = (rocketchip / Keys.libraryDependencies)
lazy val midasTargetUtils = ProjectRef(firesimDir, "targetutils")
lazy val testchipip = (project in file("generators/testchipip"))
- .dependsOn(rocketchip, sifive_blocks)
+ .dependsOn(rocketchip, rocketchip_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
@@ -180,7 +180,7 @@ lazy val fft_generator = (project in file("generators/fft-generator"))
.settings(commonSettings)
lazy val tracegen = (project in file("generators/tracegen"))
- .dependsOn(testchipip, rocketchip, sifive_cache, boom)
+ .dependsOn(testchipip, rocketchip, rocketchip_inclusive_cache, boom)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
@@ -279,12 +279,12 @@ lazy val rocket_dsp_utils = freshProject("rocket-dsp-utils", file("./tools/rocke
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sifive_blocks = (project in file("generators/sifive-blocks"))
+lazy val rocketchip_blocks = (project in file("generators/rocket-chip-blocks"))
.dependsOn(rocketchip)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
-lazy val sifive_cache = (project in file("generators/sifive-cache"))
+lazy val rocketchip_inclusive_cache = (project in file("generators/rocket-chip-inclusive-cache"))
.settings(
commonSettings,
Compile / scalaSource := baseDirectory.value / "design/craft")
@@ -304,7 +304,7 @@ lazy val firechip = (project in file("generators/firechip"))
Test / testOptions += Tests.Argument("-oF")
)
lazy val fpga_shells = (project in file("./fpga/fpga-shells"))
- .dependsOn(rocketchip, sifive_blocks)
+ .dependsOn(rocketchip, rocketchip_blocks)
.settings(libraryDependencies ++= rocketLibDeps.value)
.settings(commonSettings)
diff --git a/common.mk b/common.mk
index f525b526..3763584f 100644
--- a/common.mk
+++ b/common.mk
@@ -57,7 +57,8 @@ HELP_COMMANDS += \
" firrtl = generate intermediate firrtl files from chisel elaboration" \
" run-tests = run all assembly and benchmark tests" \
" launch-sbt = start sbt terminal" \
-" find-config-fragments = list all config. fragments"
+" find-config-fragments = list all config. fragments" \
+" check-submodule-status = check that all submodules in generators/ have been initialized"
#########################################################################################
# include additional subproject make fragments
@@ -83,6 +84,8 @@ endif
# Returns a list of files in directories $1 with *any* of the file extensions in $2
lookup_srcs_by_multiple_type = $(foreach type,$(2),$(call lookup_srcs,$(1),$(type)))
+CHECK_SUBMODULES_COMMAND = echo "Checking all submodules in generators/ are initialized. Uninitialized submodules will be displayed" ; ! git submodule status $(base_dir)/generators | grep ^-
+
SCALA_EXT = scala
VLOG_EXT = sv v
CHIPYARD_SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim fpga/fpga-shells fpga/src)
@@ -119,6 +122,7 @@ $(BOOTROM_TARGETS): $(build_dir)/bootrom.%.img: $(TESTCHIP_RSRCS_DIR)/testchipip
# compile scala jars
#########################################################################################
$(CHIPYARD_CLASSPATH_TARGETS) &: $(CHIPYARD_SCALA_SOURCES) $(SCALA_BUILDTOOL_DEPS) $(CHIPYARD_VLOG_SOURCES)
+ $(CHECK_SUBMODULES_COMMAND)
mkdir -p $(dir $@)
$(call run_sbt_assembly,$(SBT_PROJECT),$(CHIPYARD_CLASSPATH))
@@ -451,6 +455,14 @@ find-config-fragments:
help:
@for line in $(HELP_LINES); do echo "$$line"; done
+#########################################################################################
+# Check submodule status
+#########################################################################################
+
+.PHONY: check-submodule-status
+check-submodule-status:
+ $(CHECK_SUBMODULES_COMMAND)
+
#########################################################################################
# Implicit rule handling
#########################################################################################
diff --git a/docs/Chipyard-Basics/Chipyard-Components.rst b/docs/Chipyard-Basics/Chipyard-Components.rst
index 8f8e9045..669bfdfc 100644
--- a/docs/Chipyard-Basics/Chipyard-Components.rst
+++ b/docs/Chipyard-Basics/Chipyard-Components.rst
@@ -53,9 +53,9 @@ System Components:
**icenet**
A Network Interface Controller (NIC) designed to achieve up to 200 Gbps.
-**sifive-blocks**
- System components implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
- These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
+**rocket-chip-blocks**
+ System components originally implemented by SiFive and used by SiFive projects, designed to be integrated with the Rocket Chip generator.
+ Now maintained by Chips Alliance. These system and peripheral components include UART, SPI, JTAG, I2C, PWM, and other peripheral and interface devices.
**AWL (Analog Widget Library)**
Digital components required for integration with high speed serial links.
@@ -106,6 +106,9 @@ Software
FireMarshal is the default workload generation tool that Chipyard uses to create software to run on its platforms.
See :ref:`fire-marshal` for more information.
+**Baremetal-IDE**
+ Baremetal-IDE is an all-in-one tool for baremetal-level C/C++ program development. See `Tutorial `_ for more information.
+
Sims
-------------------------------------------
diff --git a/docs/Chipyard-Basics/Initial-Repo-Setup.rst b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
index 9f31624e..948b7e2e 100644
--- a/docs/Chipyard-Basics/Initial-Repo-Setup.rst
+++ b/docs/Chipyard-Basics/Initial-Repo-Setup.rst
@@ -46,7 +46,7 @@ This is done by the following:
.. code-block:: shell
- conda install -n base conda-lock=1.4
+ conda install -n base conda-lock==1.4.0
conda activate base
diff --git a/docs/Customization/Custom-Chisel.rst b/docs/Customization/Custom-Chisel.rst
index 121ca712..a3b4ef72 100644
--- a/docs/Customization/Custom-Chisel.rst
+++ b/docs/Customization/Custom-Chisel.rst
@@ -59,7 +59,7 @@ should look something like this:
.. code-block:: scala
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
sha3, dsptools, `rocket-dsp-utils`,
gemmini, icenet, tracegen, cva6, nvdla, sodor, ibex, fft_generator,
yourproject, // <- added to the middle of the list for simplicity
diff --git a/docs/Customization/Memory-Hierarchy.rst b/docs/Customization/Memory-Hierarchy.rst
index ecb666d1..11bc132b 100644
--- a/docs/Customization/Memory-Hierarchy.rst
+++ b/docs/Customization/Memory-Hierarchy.rst
@@ -46,17 +46,17 @@ agents and MMIO peripherals. Ordinarily, it is a fully-connected crossbar, but
a network-on-chip-based implementation can be generated using Constellation.
See :ref:`Customization/NoC-SoCs:SoCs with NoC-based Interconnects` for more.
-The SiFive L2 Cache
--------------------
+The Inclusive Last-Level Cache
+---------------------------------
-The default ``RocketConfig`` provided in the Chipyard example project uses SiFive's
+The default ``RocketConfig`` provided in the Chipyard example project uses the Rocket-Chip
InclusiveCache generator to produce a shared L2 cache. In the default
configuration, the L2 uses a single cache bank with 512 KiB capacity and 8-way
set-associativity. However, you can change these parameters to obtain your
desired cache configuration. The main restriction is that the number of ways
and the number of banks must be powers of 2.
-Refer to the ``CacheParameters`` object defined in sifive-cache for
+Refer to the ``CacheParameters`` object defined in ``rocket-chip-inclusive-cache`` for
customization options.
The Broadcast Hub
diff --git a/docs/Generators/SiFive-Generators.rst b/docs/Generators/Rocket-Chip-Generators.rst
similarity index 72%
rename from docs/Generators/SiFive-Generators.rst
rename to docs/Generators/Rocket-Chip-Generators.rst
index d6b174ef..435fa1dd 100644
--- a/docs/Generators/SiFive-Generators.rst
+++ b/docs/Generators/Rocket-Chip-Generators.rst
@@ -1,19 +1,19 @@
-SiFive Generators
-==================
+Rocket-Chip Generators
+======================
-Chipyard includes several open-source generators developed and maintained by `SiFive `__.
-These are currently organized within two submodules named ``sifive-blocks`` and ``sifive-cache``.
+Chipyard includes several open-source generators developed by `SiFive `__, and now openly maintained as part of Chips Alliance.
+These are currently organized within two submodules named ``rocket-chip-blocks`` and ``rocket-chip-inclusive-cache``.
Last-Level Cache Generator
-----------------------------
-``sifive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
+``rocket-chip-inclusive-cache`` includes last-level cache geneator. The Chipyard framework uses this last-level cache as an L2 cache. To use this L2 cache, you should add the ``freechips.rocketchip.subsystem.WithInclusiveCache`` config fragment to your SoC configuration.
To learn more about configuring this L2 cache, please refer to the :ref:`memory-hierarchy` section.
Peripheral Devices Overview
----------------------------
-``sifive-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
+``rocket-chip-blocks`` includes multiple peripheral device generators, such as UART, SPI, PWM, JTAG, GPIO and more.
These peripheral devices usually affect the memory map of the SoC, and its top-level IO as well.
All the peripheral blocks comes with a default memory address that would not collide with each other, but if integrating multiple duplicated blocks in the SoC is needed, you will need to explicitly specify an approriate memory address for that device.
@@ -34,7 +34,7 @@ Finally, you add the relevant config fragment to the SoC config. For example:
General Purpose I/Os (GPIO) Device
----------------------------------
-GPIO device is a periphery device provided by ``sifive-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
+GPIO device is a periphery device provided by ``rocket-chip-blocks``. Each general-purpose I/O port has five 32-bit configuration registers, two 32-bit data registers controlling pin input and output values, and eight 32-bit interrupt control/status register for signal level and edge triggering. In addition, all GPIOs can have two 32-bit alternate function selection registers.
GPIO main features
@@ -78,7 +78,7 @@ Including GPIO in the SoC
Universal Asynchronous Receiver/Transmitter (UART) Device
----------------------------------------------------------
-UART device is a periphery device provided by ``sifive-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
+UART device is a periphery device provided by ``rocket-chip-blocks``. The UART offers a flexible means to perform Full-duplex data exchange with external devices. A very wide range of baud rates can be achieved through a fractional baud rate generator. The UART peripheral does not support other modem control signals, or synchronous serial data transfers.
UART main features
@@ -125,7 +125,7 @@ Including UART in the SoC
Inter-Integrated Circuit (I2C) Interface Device
-------------------------------------------------
-I2C device is a periphery device provided by ``sifive-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
+I2C device is a periphery device provided by ``rocket-chip-blocks``. The I2C (inter-integrated circuit) bus interface handles communications to the serial I2C bus. It provides multi-master capability, and controls all I2C bus-specific sequencing, protocol, arbitration and timing. It supports Standard-mode (Sm), Fast-mode (Fm) and Fast-mode Plus (Fm+).
I2C main features
@@ -169,7 +169,7 @@ Including I2C in the SoC
Serial Peripheral Interface (SPI) Device
-------------------------------------------------
-SPI device is a periphery device provided by ``sifive-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
+SPI device is a periphery device provided by ``rocket-chip-blocks``. The SPI interface can be used to communicate with external devices using the SPI protocol.
The serial peripheral interface (SPI) protocol supports half-duplex, full-duplex and simplex synchronous, serial communication with external devices. The interface can be configured as master and in this case it provides the communication clock (SCLK) to the external slave device.
diff --git a/docs/Generators/Rocket-Chip.rst b/docs/Generators/Rocket-Chip.rst
index 856d01e1..3e404939 100644
--- a/docs/Generators/Rocket-Chip.rst
+++ b/docs/Generators/Rocket-Chip.rst
@@ -1,8 +1,8 @@
Rocket Chip
===========
-Rocket Chip generator is an SoC generator developed at Berkeley and now supported by
-`SiFive `__. Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
+Rocket Chip generator is an SoC generator developed at Berkeley and SiFive, and now maintained openly in Chips Alliance.
+Chipyard uses the Rocket Chip generator as the basis for producing a RISC-V SoC.
`Rocket Chip` is distinct from `Rocket core`, the in-order RISC-V CPU generator.
Rocket Chip includes many parts of the SoC besides the CPU. Though Rocket Chip
diff --git a/docs/Generators/Rocket.rst b/docs/Generators/Rocket.rst
index 6c55b761..536d6991 100644
--- a/docs/Generators/Rocket.rst
+++ b/docs/Generators/Rocket.rst
@@ -1,7 +1,7 @@
Rocket Core
====================================
-`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and currently supported by `SiFive `__. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
+`Rocket `__ is a 5-stage in-order scalar processor core generator, originally developed at UC Berkeley and `SiFive `__, and now maintained by Chips Alliance. The `Rocket core` is used as a component within the `Rocket Chip SoC generator`. A Rocket core combined with L1 caches (data and instruction caches) form a `Rocket tile`. The `Rocket tile` is the replicable component of the `Rocket Chip SoC generator`.
The Rocket core supports the open-source RV64GC RISC-V instruction set and is written in the Chisel hardware construction language.
It has an MMU that supports page-based virtual memory, a non-blocking data cache, and a front-end with branch prediction.
diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst
index c2bf3719..651a6bae 100644
--- a/docs/Generators/index.rst
+++ b/docs/Generators/index.rst
@@ -26,7 +26,7 @@ so changes to the generators themselves will automatically be used when building
Gemmini
IceNet
TestChipIP
- SiFive-Generators
+ Rocket-Chip-Generators
SHA3
CVA6
Ibex
diff --git a/fpga/Makefile b/fpga/Makefile
index cfe760f4..a4d3bf99 100644
--- a/fpga/Makefile
+++ b/fpga/Makefile
@@ -137,7 +137,7 @@ include $(base_dir)/common.mk
# copy from other directory
#########################################################################################
all_vsrcs := \
- $(base_dir)/generators/sifive-blocks/vsrc/SRLatch.v
+ $(base_dir)/generators/rocket-chip-blocks/vsrc/SRLatch.v
#########################################################################################
# vivado rules
diff --git a/fpga/fpga-shells b/fpga/fpga-shells
index a6cfb6f3..93004b7b 160000
--- a/fpga/fpga-shells
+++ b/fpga/fpga-shells
@@ -1 +1 @@
-Subproject commit a6cfb6f36378de7b0fd760d79f5518af7d2bba66
+Subproject commit 93004b7bd02eb7cc32a25cc1bc40595b93add118
diff --git a/fpga/src/main/scala/arty/Configs.scala b/fpga/src/main/scala/arty/Configs.scala
index e86140eb..7f10b174 100644
--- a/fpga/src/main/scala/arty/Configs.scala
+++ b/fpga/src/main/scala/arty/Configs.scala
@@ -30,6 +30,7 @@ class WithArtyTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(32) ++
new chipyard.config.WithControlBusFrequency(32) ++
new chipyard.config.WithPeripheryBusFrequency(32) ++
+ new chipyard.config.WithControlBusFrequency(32) ++
new testchipip.serdes.WithNoSerialTL ++
new testchipip.soc.WithNoScratchpads
)
diff --git a/fpga/src/main/scala/arty100t/Configs.scala b/fpga/src/main/scala/arty100t/Configs.scala
index d3879a13..bb4b8e22 100644
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
// don't use FPGAShell's DesignKey
class WithNoDesignKey extends Config((site, here, up) => {
- case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+ case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
})
// By default, this uses the on-board USB-UART for the TSI-over-UART link
diff --git a/fpga/src/main/scala/arty100t/Harness.scala b/fpga/src/main/scala/arty100t/Harness.scala
index 577bd1b2..30601124 100644
--- a/fpga/src/main/scala/arty100t/Harness.scala
+++ b/fpga/src/main/scala/arty100t/Harness.scala
@@ -5,12 +5,12 @@ import chisel3.util._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
-import freechips.rocketchip.prci.{ClockBundle, ClockBundleParameters}
+import freechips.rocketchip.prci._
import freechips.rocketchip.subsystem.{SystemBusKey}
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.blocks.devices.uart._
@@ -76,6 +76,9 @@ class Arty100THarness(override implicit val p: Parameters) extends Arty100TShell
def referenceReset = dutClock.in.head._1.reset
def success = { require(false, "Unused"); false.B }
+ childClock := harnessBinderClock
+ childReset := harnessBinderReset
+
ddrOverlay.mig.module.clock := harnessBinderClock
ddrOverlay.mig.module.reset := harnessBinderReset
ddrBlockDuringReset.module.clock := harnessBinderClock
diff --git a/fpga/src/main/scala/nexysvideo/Configs.scala b/fpga/src/main/scala/nexysvideo/Configs.scala
index fe53b96d..ce8fbae8 100644
--- a/fpga/src/main/scala/nexysvideo/Configs.scala
+++ b/fpga/src/main/scala/nexysvideo/Configs.scala
@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}
// don't use FPGAShell's DesignKey
class WithNoDesignKey extends Config((site, here, up) => {
- case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+ case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
})
// DOC include start: WithNexysVideoTweaks and Rocket
@@ -60,6 +60,7 @@ class WithTinyNexysVideoTweaks extends Config(
new chipyard.config.WithFrontBusFrequency(50.0) ++
new chipyard.config.WithSystemBusFrequency(50.0) ++
new chipyard.config.WithPeripheryBusFrequency(50.0) ++
+ new chipyard.config.WithControlBusFrequency(50.0) ++
new chipyard.harness.WithAllClocksFromHarnessClockInstantiator ++
new chipyard.clocking.WithPassthroughClockGenerator ++
new chipyard.config.WithNoDebug ++ // no jtag
diff --git a/fpga/src/main/scala/nexysvideo/Harness.scala b/fpga/src/main/scala/nexysvideo/Harness.scala
index a68cf24e..c9583f0e 100644
--- a/fpga/src/main/scala/nexysvideo/Harness.scala
+++ b/fpga/src/main/scala/nexysvideo/Harness.scala
@@ -7,10 +7,10 @@ import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart._
diff --git a/fpga/src/main/scala/vc707/TestHarness.scala b/fpga/src/main/scala/vc707/TestHarness.scala
index 1ed7ab33..317dedf6 100644
--- a/fpga/src/main/scala/vc707/TestHarness.scala
+++ b/fpga/src/main/scala/vc707/TestHarness.scala
@@ -7,11 +7,12 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.subsystem.{SystemBusKey}
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx.{VC707Shell, UARTVC707ShellPlacer, PCIeVC707ShellPlacer, ChipLinkVC707PlacedOverlay}
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks.{PLLFactoryKey}
import sifive.fpgashells.devices.xilinx.xilinxvc707pciex1.{XilinxVC707PCIeX1IO}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
@@ -87,6 +88,7 @@ class VC707FPGATestHarness(override implicit val p: Parameters) extends VC707She
}
class VC707FPGATestHarnessImp(_outer: VC707FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+ override def provideImplicitClockToLazyChildren = true
val vc707Outer = _outer
val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/Configs.scala b/fpga/src/main/scala/vcu118/Configs.scala
index 3f99fdb9..ff46deee 100644
--- a/fpga/src/main/scala/vcu118/Configs.scala
+++ b/fpga/src/main/scala/vcu118/Configs.scala
@@ -48,6 +48,7 @@ class WithVCU118Tweaks extends Config(
new chipyard.config.WithSystemBusFrequency(100) ++
new chipyard.config.WithControlBusFrequency(100) ++
new chipyard.config.WithPeripheryBusFrequency(100) ++
+ new chipyard.config.WithControlBusFrequency(100) ++
new WithFPGAFrequency(100) ++ // default 100MHz freq
// harness binders
new WithUART ++
diff --git a/fpga/src/main/scala/vcu118/CustomOverlays.scala b/fpga/src/main/scala/vcu118/CustomOverlays.scala
index 02669b79..473a015d 100644
--- a/fpga/src/main/scala/vcu118/CustomOverlays.scala
+++ b/fpga/src/main/scala/vcu118/CustomOverlays.scala
@@ -5,7 +5,7 @@ import chisel3._
import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.tilelink.{TLInwardNode, TLAsyncCrossingSink}
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell.xilinx._
@@ -79,7 +79,7 @@ class DDR2VCU118PlacedOverlay(val shell: VCU118FPGATestHarness, name: String, va
ui.reset := /*!port.mmcm_locked ||*/ port.c0_ddr4_ui_clk_sync_rst
port.c0_sys_clk_i := sys.clock.asUInt
port.sys_rst := sys.reset // pllReset
- port.c0_ddr4_aresetn := !ar.reset
+ port.c0_ddr4_aresetn := !(ar.reset.asBool)
// This was just copied from the SiFive example, but it's hard to follow.
// The pins are emitted in the following order:
diff --git a/fpga/src/main/scala/vcu118/TestHarness.scala b/fpga/src/main/scala/vcu118/TestHarness.scala
index 733c5167..78dee3e6 100644
--- a/fpga/src/main/scala/vcu118/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/TestHarness.scala
@@ -8,11 +8,11 @@ import org.chipsalliance.cde.config.{Parameters}
import freechips.rocketchip.tilelink._
import freechips.rocketchip.diplomacy.{IdRange, TransferSizes}
import freechips.rocketchip.subsystem.{SystemBusKey}
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx.{IBUF, PowerOnResetFPGAOnly}
import sifive.fpgashells.shell._
-import sifive.fpgashells.clocks.{ClockGroup, ClockSinkNode, PLLFactoryKey, ResetWrangler}
+import sifive.fpgashells.clocks._
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTPortIO}
import sifive.blocks.devices.spi.{PeripherySPIKey, SPIPortIO}
@@ -90,6 +90,7 @@ class VCU118FPGATestHarness(override implicit val p: Parameters) extends VCU118S
}
class VCU118FPGATestHarnessImp(_outer: VCU118FPGATestHarness) extends LazyRawModuleImp(_outer) with HasHarnessInstantiators {
+ override def provideImplicitClockToLazyChildren = true
val vcu118Outer = _outer
val reset = IO(Input(Bool())).suggestName("reset")
diff --git a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
index 94d28258..3de1e595 100644
--- a/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
+++ b/fpga/src/main/scala/vcu118/bringup/TestHarness.scala
@@ -5,7 +5,7 @@ import freechips.rocketchip.diplomacy._
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
import freechips.rocketchip.tilelink._
-
+import freechips.rocketchip.prci._
import sifive.fpgashells.shell.xilinx._
import sifive.fpgashells.ip.xilinx._
import sifive.fpgashells.shell._
diff --git a/generators/bar-fetchers b/generators/bar-fetchers
index a5bd985d..12d1506f 160000
--- a/generators/bar-fetchers
+++ b/generators/bar-fetchers
@@ -1 +1 @@
-Subproject commit a5bd985d29b07940e326d78964b370fa1cefec71
+Subproject commit 12d1506f610048906d2407b40a706923cbe6571e
diff --git a/generators/boom b/generators/boom
index 96da674b..9459af0c 160000
--- a/generators/boom
+++ b/generators/boom
@@ -1 +1 @@
-Subproject commit 96da674bc97955e7fa068f0a9a1d0a7a479d1d0b
+Subproject commit 9459af0c1f6847f8411622dac770ac78fe10847c
diff --git a/generators/caliptra-aes-acc b/generators/caliptra-aes-acc
index 82fa7080..8bcd6b6b 160000
--- a/generators/caliptra-aes-acc
+++ b/generators/caliptra-aes-acc
@@ -1 +1 @@
-Subproject commit 82fa7080f428b2e59062a55e948f507805c98ef5
+Subproject commit 8bcd6b6bc118e7bb493ed7cf2fed0472624f9093
diff --git a/generators/chipyard/src/main/scala/ChipTop.scala b/generators/chipyard/src/main/scala/ChipTop.scala
index 20709667..d80d71af 100644
--- a/generators/chipyard/src/main/scala/ChipTop.scala
+++ b/generators/chipyard/src/main/scala/ChipTop.scala
@@ -5,7 +5,6 @@ import chisel3._
import scala.collection.mutable.{ArrayBuffer}
import freechips.rocketchip.prci.{ClockGroupIdentityNode, ClockSinkParameters, ClockSinkNode, ClockGroup}
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey}
import org.chipsalliance.cde.config.{Parameters, Field}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, LazyRawModuleImp, LazyModuleImpLike, BindingScope}
import freechips.rocketchip.util.{DontTouch}
diff --git a/generators/chipyard/src/main/scala/DigitalTop.scala b/generators/chipyard/src/main/scala/DigitalTop.scala
index 01b6626d..879ede57 100644
--- a/generators/chipyard/src/main/scala/DigitalTop.scala
+++ b/generators/chipyard/src/main/scala/DigitalTop.scala
@@ -33,6 +33,7 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with chipyard.example.CanHavePeripheryStreamingPassthrough // Enables optionally adding the DSPTools streaming-passthrough example widget
with nvidia.blocks.dla.CanHavePeripheryNVDLA // Enables optionally having an NVDLA
with chipyard.clocking.HasChipyardPRCI // Use Chipyard reset/clock distribution
+ with chipyard.clocking.CanHaveClockTap // Enables optionally adding a clock tap output port
with fftgenerator.CanHavePeripheryFFT // Enables optionally having an MMIO-based FFT block
with constellation.soc.CanHaveGlobalNoC // Support instantiating a global NoC interconnect
{
@@ -40,7 +41,6 @@ class DigitalTop(implicit p: Parameters) extends ChipyardSystem
}
class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
- with testchipip.cosim.CanHaveTraceIOModuleImp
with sifive.blocks.devices.i2c.HasPeripheryI2CModuleImp
with sifive.blocks.devices.pwm.HasPeripheryPWMModuleImp
with sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
diff --git a/generators/chipyard/src/main/scala/SpikeTile.scala b/generators/chipyard/src/main/scala/SpikeTile.scala
index fc822c22..97866c50 100644
--- a/generators/chipyard/src/main/scala/SpikeTile.scala
+++ b/generators/chipyard/src/main/scala/SpikeTile.scala
@@ -2,7 +2,7 @@ package chipyard
import chisel3._
import chisel3.util._
-import chisel3.experimental.{IntParam, StringParam, IO}
+import chisel3.experimental.{IntParam, StringParam}
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
@@ -77,14 +77,15 @@ case class SpikeTileAttachParams(
}
case class SpikeTileParams(
- hartId: Int = 0,
+ tileId: Int = 0,
val core: SpikeCoreParams = SpikeCoreParams(),
icacheParams: ICacheParams = ICacheParams(nWays = 32),
dcacheParams: DCacheParams = DCacheParams(nWays = 32),
tcmParams: Option[MasterPortParams] = None // tightly coupled memory
) extends InstantiableTileParams[SpikeTile]
{
- val name = Some("spike_tile")
+ val baseName = "spike_tile"
+ val uniqueName = s"${baseName}_$tileId"
val beuAddr = None
val blockerCtrlAddr = None
val btb = None
@@ -92,7 +93,7 @@ case class SpikeTileParams(
val dcache = Some(dcacheParams)
val icache = Some(icacheParams)
val clockSinkParams = ClockSinkParameters()
- def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
+ def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): SpikeTile = {
new SpikeTile(this, crossing, lookup)
}
}
@@ -106,11 +107,11 @@ class SpikeTile(
with SourcesExternalNotifications
{
// Private constructor ensures altered LazyModule.p is used implicitly
- def this(params: SpikeTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+ def this(params: SpikeTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
// Required TileLink nodes
- val intOutwardNode = IntIdentityNode()
+ val intOutwardNode = None
val masterNode = visibilityNode
val slaveNode = TLIdentityNode()
@@ -129,21 +130,21 @@ class SpikeTile(
}
ResourceBinding {
- Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+ Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
}
val icacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
sourceId = IdRange(0, 1),
- name = s"Core ${staticIdForMetadataUseOnly} ICache")))))
+ name = s"Core ${tileId} ICache")))))
val dcacheNode = TLClientNode(Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
- name = s"Core ${staticIdForMetadataUseOnly} DCache",
+ name = s"Core ${tileId} DCache",
sourceId = IdRange(0, tileParams.dcache.get.nMSHRs),
supportsProbe = TransferSizes(p(CacheBlockBytes), p(CacheBlockBytes)))))))
val mmioNode = TLClientNode((Seq(TLMasterPortParameters.v1(Seq(TLMasterParameters.v1(
- name = s"Core ${staticIdForMetadataUseOnly} MMIO",
+ name = s"Core ${tileId} MMIO",
sourceId = IdRange(0, 1),
requestFifo = true))))))
@@ -313,7 +314,7 @@ class SpikeBlackBox(
}
class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
-
+ val tileParams = outer.tileParams
// We create a bundle here and decode the interrupt.
val int_bundle = Wire(new TileInterrupts())
outer.decodeCoreInterrupts(int_bundle)
@@ -337,7 +338,7 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
// then the DTM-based bringup with SimDTM will be used. This isn't required to be
// true, but it usually is
val useDTM = p(ExportDebug).protocols.contains(DMI)
- val spike = Module(new SpikeBlackBox(hartId, isaDTS, tileParams.core.nPMPs,
+ val spike = Module(new SpikeBlackBox(outer.tileId, outer.isaDTS, tileParams.core.nPMPs,
tileParams.icache.get.nSets, tileParams.icache.get.nWays,
tileParams.dcache.get.nSets, tileParams.dcache.get.nWays,
tileParams.dcache.get.nMSHRs,
@@ -467,19 +468,21 @@ class SpikeTileModuleImp(outer: SpikeTile) extends BaseTileModuleImp(outer) {
}
}
-class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams(),
- overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNSpikeCores(n: Int = 1, tileParams: SpikeTileParams = SpikeTileParams()
+) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
// Calculate the next available hart ID (since hart ID cannot be duplicated)
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
// Create TileAttachParams for every core to be instantiated
(0 until n).map { i =>
SpikeTileAttachParams(
- tileParams = tileParams.copy(hartId = i + idOffset)
+ tileParams = tileParams.copy(tileId = i + idOffset)
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
+
})
class WithSpikeTCM extends Config((site, here, up) => {
@@ -492,5 +495,5 @@ class WithSpikeTCM extends Config((site, here, up) => {
)))
}
case ExtMem => None
- case BankedL2Key => up(BankedL2Key).copy(nBanks = 0)
+ case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey).copy(nBanks = 0)
})
diff --git a/generators/chipyard/src/main/scala/Subsystem.scala b/generators/chipyard/src/main/scala/Subsystem.scala
index 8654d561..993dad02 100644
--- a/generators/chipyard/src/main/scala/Subsystem.scala
+++ b/generators/chipyard/src/main/scala/Subsystem.scala
@@ -71,18 +71,24 @@ trait CanHaveChosenInDTS { this: BaseSubsystem =>
}
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
- with HasTiles
- with HasPeripheryDebug
- with CanHaveHTIF
- with CanHaveChosenInDTS
+ with InstantiatesHierarchicalElements
+ with HasTileNotificationSinks
+ with HasTileInputConstants
+ with CanHavePeripheryCLINT
+ with CanHavePeripheryPLIC
+ with HasPeripheryDebug
+ with HasHierarchicalElementsRootContext
+ with HasHierarchicalElements
+ with CanHaveHTIF
+ with CanHaveChosenInDTS
{
- def coreMonitorBundles = tiles.map {
+ def coreMonitorBundles = totalTiles.values.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle
}.toList
// No-tile configs have to be handled specially.
- if (tiles.size == 0) {
+ if (totalTiles.size == 0) {
// no PLIC, so sink interrupts to nowhere
require(!p(PLICKey).isDefined)
val intNexus = IntNexusNode(sourceFn = x => x.head, sinkFn = x => x.head)
@@ -90,16 +96,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
intSink := intNexus :=* ibus.toPLIC
// avoids a bug when there are no interrupt sources
- ibus.fromAsync := NullIntSource()
+ ibus { ibus.fromAsync := NullIntSource() }
// Need to have at least 1 driver to the tile notification sinks
tileHaltXbarNode := IntSourceNode(IntSourcePortSimple())
tileWFIXbarNode := IntSourceNode(IntSourcePortSimple())
tileCeaseXbarNode := IntSourceNode(IntSourcePortSimple())
-
- // Sink reset vectors to nowhere
- val resetVectorSink = BundleBridgeSink[UInt](Some(() => UInt(28.W)))
- resetVectorSink := tileResetVectorNode
}
// Relying on [[TLBusWrapperConnection]].driveClockFromMaster for
@@ -107,7 +109,7 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
// ClockGroup. This makes it impossible to determine which clocks are driven
// by which bus based on the member names, which is problematic when there is
// a rational crossing between two buses. Instead, provide all bus clocks
- // directly from the asyncClockGroupsNode in the subsystem to ensure bus
+ // directly from the allClockGroupsNode in the subsystem to ensure bus
// names are always preserved in the top-level clock names.
//
// For example, using a RationalCrossing between the Sbus and Cbus, and
@@ -116,12 +118,12 @@ class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
// Conversly, if an async crossing is used, they instead receive names of the
// form "subsystem_cbus_[0-9]*". The assignment below provides the latter names in all cases.
Seq(PBUS, FBUS, MBUS, CBUS).foreach { loc =>
- tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := asyncClockGroupsNode }
+ tlBusWrapperLocationMap.lift(loc).foreach { _.clockGroupNode := allClockGroupsNode }
}
override lazy val module = new ChipyardSubsystemModuleImp(this)
}
class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
- with HasTilesModuleImp
+ with HasHierarchicalElementsRootContextModuleImp
{
}
diff --git a/generators/chipyard/src/main/scala/System.scala b/generators/chipyard/src/main/scala/System.scala
index 5643e380..b8a04eac 100644
--- a/generators/chipyard/src/main/scala/System.scala
+++ b/generators/chipyard/src/main/scala/System.scala
@@ -32,13 +32,6 @@ class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
val bootROM = p(BootROMLocated(location)).map { BootROM.attach(_, this, CBUS) }
val maskROMs = p(MaskROMLocated(location)).map { MaskROM.attach(_, this, CBUS) }
- // If there is no bootrom, the tile reset vector bundle will be tied to zero
- if (bootROM.isEmpty) {
- val fakeResetVectorSourceNode = BundleBridgeSource[UInt]()
- InModuleBody { fakeResetVectorSourceNode.bundle := 0.U }
- tileResetVectorNexusNode := fakeResetVectorSourceNode
- }
-
override lazy val module = new ChipyardSystemModule(this)
}
diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala
index 0e4e3310..2a88ebb2 100644
--- a/generators/chipyard/src/main/scala/TestSuites.scala
+++ b/generators/chipyard/src/main/scala/TestSuites.scala
@@ -65,7 +65,7 @@ class TestSuiteHelper
*/
def addGenericTestSuites(tiles: Seq[TileParams])(implicit p: Parameters) = {
val xlen = p(XLen)
- tiles.find(_.hartId == 0).map { tileParams =>
+ tiles.find(_.tileId == 0).map { tileParams =>
val coreParams = tileParams.core
val vm = coreParams.useVM
val env = if (vm) List("p","v") else List("p")
diff --git a/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
new file mode 100644
index 00000000..5d0ce538
--- /dev/null
+++ b/generators/chipyard/src/main/scala/clocking/CanHaveClockTap.scala
@@ -0,0 +1,27 @@
+package chipyard.clocking
+
+import chisel3._
+
+import org.chipsalliance.cde.config.{Parameters, Field, Config}
+import freechips.rocketchip.diplomacy._
+import freechips.rocketchip.tilelink._
+import freechips.rocketchip.subsystem._
+import freechips.rocketchip.util._
+import freechips.rocketchip.tile._
+import freechips.rocketchip.prci._
+
+case object ClockTapKey extends Field[Boolean](true)
+
+trait CanHaveClockTap { this: BaseSubsystem =>
+ require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+ val clockTapNode = Option.when(p(ClockTapKey)) {
+ val clockTap = ClockSinkNode(Seq(ClockSinkParameters(name=Some("clock_tap"))))
+ clockTap := ClockGroup() := asyncClockGroupsNode
+ clockTap
+ }
+ val clockTapIO = clockTapNode.map { node => InModuleBody {
+ val clock_tap = IO(Output(Clock()))
+ clock_tap := node.in.head._1.clock
+ clock_tap
+ }}
+}
diff --git a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
index 36d1fa2f..fdb2ec9e 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockBinders.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chipyard.iobinders.{OverrideLazyIOBinder, GetSystemParameters, IOCellKey, ClockPort, ResetPort}
+import chipyard.iobinders._
import freechips.rocketchip.prci._
import freechips.rocketchip.diplomacy._
import freechips.rocketchip.subsystem._
@@ -14,31 +14,24 @@ import barstools.iocell.chisel._
// blocks, which allow memory-mapped control of clock division, and clock muxing
// between the FakePLL and the slow off-chip clock
// Note: This will not simulate properly with firesim
-class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
+// Unsetting enable will prevent the divider/selector from actually modifying the clock,
+// while preserving the address map. Unsetting enable should only be done for RTL
+// simulators (Verilator) which do not model reset properly
+class WithPLLSelectorDividerClockGenerator(enable: Boolean = true) extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
// Connect the implicit clock
implicit val p = GetSystemParameters(system)
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
- InModuleBody {
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
- }
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
- val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
- val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes)) }
+ val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes, enable=enable)) }
+ val clockSelector = system.prci_ctrl_domain { LazyModule(new TLClockSelector(baseAddress + 0x30000, tlbus.beatBytes, enable=enable)) }
val pllCtrl = system.prci_ctrl_domain { LazyModule(new FakePLLCtrl (baseAddress + 0x40000, tlbus.beatBytes)) }
clockDivider.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
clockSelector.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
pllCtrl.tlNode := system.prci_ctrl_domain { TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := system.prci_ctrl_bus.get }
- system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+ system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -83,23 +76,12 @@ class WithPLLSelectorDividerClockGenerator extends OverrideLazyIOBinder({
// This passes all clocks through to the TestHarness
class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
(system: HasChipyardPRCI) => {
- // Connect the implicit clock
implicit val p = GetSystemParameters(system)
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
- InModuleBody {
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.asInstanceOf[BaseSubsystem].module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
- }
// This aggregate node should do nothing
val clockGroupAggNode = ClockGroupAggregateNode("fake")
val clockGroupsSourceNode = ClockGroupSourceNode(Seq(ClockGroupSourceParameters()))
- system.allClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
+ system.chiptopClockGroupsNode := clockGroupAggNode := clockGroupsSourceNode
InModuleBody {
val reset_io = IO(Input(AsyncReset()))
@@ -119,3 +101,12 @@ class WithPassthroughClockGenerator extends OverrideLazyIOBinder({
}
}
})
+
+class WithClockTapIOCells extends OverrideIOBinder({
+ (system: CanHaveClockTap) => {
+ system.clockTapIO.map { tap =>
+ val (clock_tap_io, clock_tap_cell) = IOCell.generateIOFromSignal(tap.getWrappedValue, "clock_tap")
+ (Seq(ClockTapPort(() => clock_tap_io)), clock_tap_cell)
+ }.getOrElse((Nil, Nil))
+ }
+})
diff --git a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
index e5236804..9b53cbef 100644
--- a/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
+++ b/generators/chipyard/src/main/scala/clocking/ClockGroupCombiner.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
index 7aa676d5..9b140e20 100644
--- a/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
+++ b/generators/chipyard/src/main/scala/clocking/HasChipyardPRCI.scala
@@ -30,15 +30,14 @@ case class ChipyardPRCIControlParams(
case object ChipyardPRCIControlKey extends Field[ChipyardPRCIControlParams](ChipyardPRCIControlParams())
-trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
- require(p(SubsystemDriveAsyncClockGroupsKey).isEmpty, "Subsystem asyncClockGroups must be undriven")
+trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesHierarchicalElements =>
+ require(!p(SubsystemDriveClockGroupsFromIO), "Subsystem allClockGroups cannot be driven from implicit clocks")
val prciParams = p(ChipyardPRCIControlKey)
// Set up clock domain
private val tlbus = locateTLBusWrapper(prciParams.slaveWhere)
- val prci_ctrl_domain = LazyModule(new ClockSinkDomain(name=Some("chipyard-prci-control")))
- prci_ctrl_domain.clockNode := tlbus.fixedClockNode
+ val prci_ctrl_domain = tlbus.generateSynchronousDomain.suggestName("chipyard_prcictrl_domain")
val prci_ctrl_bus = Option.when(prciParams.generatePRCIXBar) { prci_ctrl_domain { TLXbar() } }
prci_ctrl_bus.foreach(xbar => tlbus.coupleTo("prci_ctrl") { (xbar
@@ -49,29 +48,13 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
// Aggregate all the clock groups into a single node
val aggregator = LazyModule(new ClockGroupAggregator("allClocks")).node
- val allClockGroupsNode = ClockGroupEphemeralNode()
- // There are two "sets" of clocks which must be dealt with
-
- // 1. The implicit clock from the subsystem. RC is moving away from depending on this
- // clock, but some modules still use it. Since the implicit clock sink node
- // is created in the ChipTop (the hierarchy wrapping the subsystem), this function
- // is provided to allow connecting that clock to the clock aggregator. This function
- // should be called in the ChipTop context
- def connectImplicitClockSinkNode(sink: ClockSinkNode) = {
- val implicitClockGrouper = this { ClockGroup() }
- (sink
- := implicitClockGrouper
- := aggregator)
- }
-
- // 2. The rest of the diplomatic clocks in the subsystem are routed to this asyncClockGroupsNode
+ // The diplomatic clocks in the subsystem are routed to this allClockGroupsNode
val clockNamePrefixer = ClockGroupNamePrefixer()
- (asyncClockGroupsNode
+ (allClockGroupsNode
:*= clockNamePrefixer
:*= aggregator)
-
// Once all the clocks are gathered in the aggregator node, several steps remain
// 1. Assign frequencies to any clock groups which did not specify a frequency.
// 2. Combine duplicated clock groups (clock groups which physically should be in the same clock domain)
@@ -92,7 +75,7 @@ trait HasChipyardPRCI { this: BaseSubsystem with InstantiatesTiles =>
} }
val tileResetSetter = Option.when(prciParams.enableTileResetSetting) { prci_ctrl_domain {
val reset_setter = LazyModule(new TileResetSetter(prciParams.baseAddress + 0x10000, tlbus.beatBytes,
- tile_prci_domains.map(_.tile_reset_domain.clockNode.portParams(0).name.get), Nil))
+ tile_prci_domains.map(_._2.tile_reset_domain.clockNode.portParams(0).name.get).toSeq, Nil))
reset_setter.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := prci_ctrl_bus.get
reset_setter
} }
@@ -116,11 +99,14 @@ RTL SIMULATORS, NAMELY VERILATOR.
""" + Console.RESET)
}
+ // The chiptopClockGroupsNode shouuld be what ClockBinders attach to
+ val chiptopClockGroupsNode = ClockGroupEphemeralNode()
+
(aggregator
:= frequencySpecifier
:= clockGroupCombiner
:= resetSynchronizer
:= tileClockGater.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
:= tileResetSetter.map(_.clockNode).getOrElse(ClockGroupEphemeralNode()(ValName("temp")))
- := allClockGroupsNode)
+ := chiptopClockGroupsNode)
}
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
index a3c33561..958c9194 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockDivider.scala
@@ -15,11 +15,27 @@ import testchipip.clocking._
// This module adds a TileLink memory-mapped clock divider to the clock graph
// The output clock/reset pairs from this module should be synchronized later
-class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will not divide the clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice(s"clk-div-ctrl", Nil)
val clockNode = ClockGroupIdentityNode()
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
+ if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKDIVIDER IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
lazy val module = new LazyModuleImp(this) {
require (clockNode.out.size == 1)
val sources = clockNode.in.head._1.member.data.toSeq
@@ -45,13 +61,21 @@ class TLClockDivider(address: BigInt, beatBytes: Int, divBits: Int = 8)(implicit
// by setting divisor=0. The divisor signal into the ClockDividerOrPass is synchronized internally
divider.io.divisor := Mux(busReset.asBool, 0.U, reg.io.q)
divider.io.resetAsync := ResetStretcher(sources(i).clock, asyncReset, 20).asAsyncReset
- sinks(i)._2.clock := divider.io.clockOut
- // Note this is not synchronized to the output clock, which takes time to appear
- // so this is still asyncreset
- // Stretch the reset for 40 cycles, to give enough time to reset any downstream
- // digital logic
- sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+ if (enable) {
+ sinks(i)._2.clock := divider.io.clockOut
+
+ // Note this is not synchronized to the output clock, which takes time to appear
+ // so this is still asyncreset
+ // Stretch the reset for 40 cycles, to give enough time to reset any downstream
+ // digital logic
+ sinks(i)._2.reset := ResetStretcher(sources(i).clock, asyncReset, 40).asAsyncReset
+ } else {
+ // WARNING: THIS IS FOR RTL SIMULATION ONLY
+ sinks(i)._2.clock := sources(i).clock
+ sinks(i)._2.reset := sources(i).reset
+ }
+
reg
}
diff --git a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
index 1d0a149d..8c6371f1 100644
--- a/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
+++ b/generators/chipyard/src/main/scala/clocking/TLClockSelector.scala
@@ -21,12 +21,30 @@ case class ClockSelNode()(implicit valName: ValName)
// This module adds a TileLink memory-mapped clock mux for each downstream clock domain
// in the clock graph. The output clock/reset should be synchronized downstream
-class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) extends LazyModule {
+// If enable is unset, this will always pass through the 0'th clock
+// DO NOT unset enable for VLSI, or prototyping flows. The disable feature is a work around for
+// some RTL simulators which do not simulate the reset synchronization properly
+class TLClockSelector(address: BigInt, beatBytes: Int, enable: Boolean = true)(implicit p: Parameters) extends LazyModule {
val device = new SimpleDevice("clk-sel-ctrl", Nil)
val tlNode = TLRegisterNode(Seq(AddressSet(address, 4096-1)), device, "reg/control", beatBytes=beatBytes)
val clockNode = ClockSelNode()
+ if (!enable) println(Console.RED + s"""
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+
+WARNING:
+
+YOU ARE USING THE TLCLOCKSELECTOR IN
+"DISABLED" MODE. THIS SHOULD ONLY BE DONE
+FOR RTL SIMULATION
+
+!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
+""" + Console.RESET)
+
+
+
lazy val module = new LazyModuleImp(this) {
val asyncReset = clockNode.in.map(_._1).map(_.reset).toSeq(0)
val clocks = clockNode.in.map(_._1).map(_.clock)
@@ -43,10 +61,15 @@ class TLClockSelector(address: BigInt, beatBytes: Int)(implicit p: Parameters) e
val mux = ClockMutexMux(clocks).suggestName(s"${sinkName}_clkmux")
mux.io.sel := sel
mux.io.resetAsync := asyncReset.asAsyncReset
- sinks(i).clock := mux.io.clockOut
- // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
- sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
-
+ if (enable) {
+ sinks(i).clock := mux.io.clockOut
+ // Stretch the reset for 20 cycles, to give time to reset any downstream digital logic
+ sinks(i).reset := ResetStretcher(clocks(0), asyncReset, 20).asAsyncReset
+ } else {
+ // WARNING: THIS IS FOR RTL SIMULATION ONLY
+ sinks(i).clock := clocks(0)
+ sinks(i).reset := asyncReset
+ }
reg
}
tlNode.regmap((0 until sinks.size).map { i =>
diff --git a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
index e299d0a9..c92e05bc 100644
--- a/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileClockGater.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
index 53dd36d0..88916d17 100644
--- a/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
+++ b/generators/chipyard/src/main/scala/clocking/TileResetSetter.scala
@@ -2,7 +2,7 @@ package chipyard.clocking
import chisel3._
import chisel3.util._
-import chisel3.experimental.{Analog, IO}
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.subsystem._
diff --git a/generators/chipyard/src/main/scala/config/AbstractConfig.scala b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
index a5d4f48a..70770491 100644
--- a/generators/chipyard/src/main/scala/config/AbstractConfig.scala
+++ b/generators/chipyard/src/main/scala/config/AbstractConfig.scala
@@ -51,10 +51,12 @@ class AbstractConfig extends Config(
new chipyard.iobinders.WithUARTTSIPunchthrough ++
new chipyard.iobinders.WithNMITiedOff ++
- // By default, punch out IOs to the Harness
- new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
+ new chipyard.clocking.WithClockTapIOCells ++ // Default generate a clock tapio
+ new chipyard.clocking.WithPassthroughClockGenerator ++ // Default punch out IOs to the Harness
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", // Default merge all the bus clocks
+ Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit", "clock_tap"), Seq("tile"))) ++
new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
+ new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
@@ -75,7 +77,7 @@ class AbstractConfig extends Config(
new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
- new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
+ new chipyard.config.WithNoSubsystemClockIO ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
index 583d40bc..52f39a03 100644
--- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala
@@ -126,5 +126,9 @@ class TetheredChipLikeRocketConfig extends Config(
class VerilatorCITetheredChipLikeRocketConfig extends Config(
new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // use absolute freqs for sims in the harness
new chipyard.harness.WithMultiChipSerialTL(0, 1) ++ // connect the serial-tl ports of the chips together
- new chipyard.harness.WithMultiChip(0, new chipyard.config.WithNoResetSynchronizers ++ new ChipLikeRocketConfig) ++
+ new chipyard.harness.WithMultiChip(0, // These fragments remove all troublesome
+ new chipyard.clocking.WithPLLSelectorDividerClockGenerator(enable=false) ++ // clocking features from the design
+ new chipyard.iobinders.WithDebugIOCells(syncReset = false) ++
+ new chipyard.config.WithNoResetSynchronizers ++
+ new ChipLikeRocketConfig) ++
new chipyard.harness.WithMultiChip(1, new ChipBringupHostConfig))
diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
index 216cb53e..0ddb3737 100644
--- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala
@@ -2,6 +2,7 @@ package chipyard
import org.chipsalliance.cde.config.{Config}
import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{InCluster}
// --------------
// Rocket Configs
@@ -62,7 +63,7 @@ class MulticlockRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
// Frequency specifications
new chipyard.config.WithTileFrequency(1000.0) ++ // Matches the maximum frequency of U540
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit"), Nil),
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore" , Seq("sbus", "cbus", "implicit", "clock_tap"), Nil),
("periphery", Seq("pbus", "fbus"), Nil)) ++
new chipyard.config.WithSystemBusFrequency(500.0) ++ // Matches the maximum frequency of U540
new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Matches the maximum frequency of U540
@@ -88,3 +89,10 @@ class PrefetchingRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithNonblockingL1(2) ++ // non-blocking L1D$, L1 prefetching only works with non-blocking L1D$
new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
new chipyard.config.AbstractConfig)
+
+class ClusteredRocketConfig extends Config(
+ new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(1)) ++
+ new freechips.rocketchip.subsystem.WithNBigCores(4, location=InCluster(0)) ++
+ new freechips.rocketchip.subsystem.WithCluster(1) ++
+ new freechips.rocketchip.subsystem.WithCluster(0) ++
+ new chipyard.config.AbstractConfig)
diff --git a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
index 4235bf1e..c9db790d 100644
--- a/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
+++ b/generators/chipyard/src/main/scala/config/TracegenConfigs.scala
@@ -12,10 +12,11 @@ class AbstractTraceGenConfig extends Config(
new chipyard.iobinders.WithAXI4MemPunchthrough ++
new chipyard.iobinders.WithTraceGenSuccessPunchthrough ++
new chipyard.clocking.WithPassthroughClockGenerator ++
- new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "implicit"), Nil)) ++
+ new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus"), Nil)) ++
new chipyard.config.WithTracegenSystem ++
- new chipyard.config.WithNoSubsystemDrivenClocks ++
+ new chipyard.config.WithNoSubsystemClockIO ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
diff --git a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
index f86254c4..8cf6ae67 100644
--- a/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/ClockingFragments.scala
@@ -19,8 +19,8 @@ import testchipip.soc.{OffchipBusKey}
// with the implicit clocks of Subsystem. Don't do that, instead we extend
// the diplomacy graph upwards into the ChipTop, where we connect it to
// our clock drivers
-class WithNoSubsystemDrivenClocks extends Config((site, here, up) => {
- case SubsystemDriveAsyncClockGroupsKey => None
+class WithNoSubsystemClockIO extends Config((site, here, up) => {
+ case SubsystemDriveClockGroupsFromIO => false
})
/**
@@ -111,14 +111,22 @@ class WithOffchipBusFrequency(freqMHz: Double) extends Config((site, here, up) =
class WithRationalMemoryBusCrossing extends WithSbusToMbusCrossingType(RationalCrossing(Symmetric))
class WithAsynchrousMemoryBusCrossing extends WithSbusToMbusCrossingType(AsynchronousCrossing())
+// Remove the tile clock gaters in this system
class WithNoTileClockGaters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileClockGating = false)
})
+// Remove the tile reset control blocks in this system
class WithNoTileResetSetters extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableTileResetSetting = false)
})
+// Remove the global reset synchronizers in this system
class WithNoResetSynchronizers extends Config((site, here, up) => {
case ChipyardPRCIControlKey => up(ChipyardPRCIControlKey).copy(enableResetSynchronizers = false)
})
+
+// Remove any ClockTap ports in this system
+class WithNoClockTap extends Config((site, here, up) => {
+ case ClockTapKey => false
+})
diff --git a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
index 4680eeeb..c9f7fcdb 100644
--- a/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/RoCCFragments.scala
@@ -12,15 +12,15 @@ import gemmini._
import chipyard.{TestSuitesKey, TestSuiteHelper}
/**
- * Map from a hartId to a particular RoCC accelerator
+ * Map from a tileId to a particular RoCC accelerator
*/
case object MultiRoCCKey extends Field[Map[Int, Seq[Parameters => LazyRoCC]]](Map.empty[Int, Seq[Parameters => LazyRoCC]])
/**
- * Config fragment to enable different RoCCs based on the hartId
+ * Config fragment to enable different RoCCs based on the tileId
*/
class WithMultiRoCC extends Config((site, here, up) => {
- case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).hartId, Nil)
+ case BuildRoCC => site(MultiRoCCKey).getOrElse(site(TileKey).tileId, Nil)
})
/**
@@ -39,7 +39,7 @@ class WithMultiRoCCFromBuildRoCC(harts: Int*) extends Config((site, here, up) =>
*
* For ex:
* Core 0, 1, 2, 3 have been defined earlier
- * with hartIds of 0, 1, 2, 3 respectively
+ * with tileIds of 0, 1, 2, 3 respectively
* And you call WithMultiRoCCHwacha(0,1)
* Then Core 0 and 1 will get a Hwacha
*
diff --git a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
index 7a45d293..b4971cba 100644
--- a/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/SubsystemFragments.scala
@@ -7,7 +7,7 @@ import sifive.blocks.inclusivecache.{InclusiveCachePortParameters}
// Replaces the L2 with a broadcast manager for maintaining coherence
class WithBroadcastManager extends Config((site, here, up) => {
- case BankedL2Key => up(BankedL2Key, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
+ case SubsystemBankedCoherenceKey => up(SubsystemBankedCoherenceKey, site).copy(coherenceManager = CoherenceManagerWrapper.broadcastManager)
})
class WithBroadcastParams(params: BroadcastParams) extends Config((site, here, up) => {
diff --git a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
index 92d8fc6f..392f1508 100644
--- a/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
+++ b/generators/chipyard/src/main/scala/config/fragments/TileFragments.scala
@@ -78,7 +78,7 @@ class WithRocketCacheRowBits(rowBits: Int = 64) extends Config((site, here, up)
class WithRocketICacheScratchpad extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
- icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.hartId * 0x10000)))
+ icache = tp.tileParams.icache.map(_.copy(itimAddr = Some(0x300000 + tp.tileParams.tileId * 0x10000)))
))
}
})
@@ -86,7 +86,7 @@ class WithRocketICacheScratchpad extends Config((site, here, up) => {
class WithRocketDCacheScratchpad extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
- dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.hartId * 0x10000)))
+ dcache = tp.tileParams.dcache.map(_.copy(nSets = 32, nWays = 1, scratch = Some(0x200000 + tp.tileParams.tileId * 0x10000)))
))
}
})
@@ -94,15 +94,15 @@ class WithRocketDCacheScratchpad extends Config((site, here, up) => {
class WithTilePrefetchers extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: BoomTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: SodorTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: IbexTileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
case tp: CVA6TileAttachParams => tp.copy(crossingParams = tp.crossingParams.copy(
- master = TilePrefetchingMasterPortParams(tp.tileParams.hartId, tp.crossingParams.master)))
+ master = TilePrefetchingMasterPortParams(tp.tileParams.tileId, tp.crossingParams.master)))
}
})
diff --git a/generators/chipyard/src/main/scala/example/FlatChipTop.scala b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
index 96139ef5..d4caa49b 100644
--- a/generators/chipyard/src/main/scala/example/FlatChipTop.scala
+++ b/generators/chipyard/src/main/scala/example/FlatChipTop.scala
@@ -30,9 +30,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
//========================
// Diplomatic clock stuff
//========================
- val implicitClockSinkNode = ClockSinkNode(Seq(ClockSinkParameters(name = Some("implicit_clock"))))
- system.connectImplicitClockSinkNode(implicitClockSinkNode)
-
val tlbus = system.locateTLBusWrapper(system.prciParams.slaveWhere)
val baseAddress = system.prciParams.baseAddress
val clockDivider = system.prci_ctrl_domain { LazyModule(new TLClockDivider (baseAddress + 0x20000, tlbus.beatBytes)) }
@@ -43,7 +40,7 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
tlbus.coupleTo("clock-sel-ctrl") { clockSelector.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
tlbus.coupleTo("pll-ctrl") { pllCtrl.tlNode := TLFragmenter(tlbus.beatBytes, tlbus.blockBytes) := TLBuffer() := _ }
- system.allClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
+ system.chiptopClockGroupsNode := clockDivider.clockNode := clockSelector.clockNode
// Connect all other requested clocks
val slowClockSource = ClockSourceNode(Seq(ClockSourceParameters()))
@@ -69,13 +66,6 @@ class FlatChipTop(implicit p: Parameters) extends LazyModule with HasChipyardPor
//=========================
// Clock/reset
//=========================
- val implicit_clock = implicitClockSinkNode.in.head._1.clock
- val implicit_reset = implicitClockSinkNode.in.head._1.reset
- system.module match { case l: LazyModuleImp => {
- l.clock := implicit_clock
- l.reset := implicit_reset
- }}
-
val clock_wire = Wire(Input(Clock()))
val reset_wire = Wire(Input(AsyncReset()))
val (clock_pad, clockIOCell) = IOCell.generateIOFromSignal(clock_wire, "clock", p(IOCellKey))
diff --git a/generators/chipyard/src/main/scala/example/GCD.scala b/generators/chipyard/src/main/scala/example/GCD.scala
index ae1d49dd..1c1d2e2f 100644
--- a/generators/chipyard/src/main/scala/example/GCD.scala
+++ b/generators/chipyard/src/main/scala/example/GCD.scala
@@ -185,7 +185,7 @@ trait CanHavePeripheryGCD { this: BaseSubsystem =>
// DOC include end: GCD lazy trait
// DOC include start: GCD imp trait
-trait CanHavePeripheryGCDModuleImp extends LazyModuleImp {
+trait CanHavePeripheryGCDModuleImp extends LazyRawModuleImp {
val outer: CanHavePeripheryGCD
val gcd_busy = outer.gcd match {
case Some(gcd) => {
diff --git a/generators/chipyard/src/main/scala/example/TutorialTile.scala b/generators/chipyard/src/main/scala/example/TutorialTile.scala
index 38c8577a..76b17273 100644
--- a/generators/chipyard/src/main/scala/example/TutorialTile.scala
+++ b/generators/chipyard/src/main/scala/example/TutorialTile.scala
@@ -82,7 +82,7 @@ case class MyTileAttachParams(
case class MyTileParams(
name: Option[String] = Some("my_tile"),
- hartId: Int = 0,
+ tileId: Int = 0,
trace: Boolean = false,
val core: MyCoreParams = MyCoreParams()
) extends InstantiableTileParams[MyTile]
@@ -94,9 +94,11 @@ case class MyTileParams(
val dcache: Option[DCacheParams] = Some(DCacheParams())
val icache: Option[ICacheParams] = Some(ICacheParams())
val clockSinkParams: ClockSinkParameters = ClockSinkParameters()
- def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
+ def instantiate(crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): MyTile = {
new MyTile(this, crossing, lookup)
}
+ val baseName = name.getOrElse("my_tile")
+ val uniqueName = s"${baseName}_$tileId"
}
// DOC include start: Tile class
@@ -111,11 +113,11 @@ class MyTile(
{
// Private constructor ensures altered LazyModule.p is used implicitly
- def this(params: MyTileParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
+ def this(params: MyTileParams, crossing: HierarchicalElementCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
// Require TileLink nodes
- val intOutwardNode = IntIdentityNode()
+ val intOutwardNode = None
val masterNode = visibilityNode
val slaveNode = TLIdentityNode()
@@ -135,7 +137,7 @@ class MyTile(
}
ResourceBinding {
- Resource(cpuDevice, "reg").bind(ResourceAddress(hartId))
+ Resource(cpuDevice, "reg").bind(ResourceAddress(tileId))
}
// TODO: Create TileLink nodes and connections here.
@@ -228,15 +230,15 @@ class MyTileModuleImp(outer: MyTile) extends BaseTileModuleImp(outer){
}
// DOC include start: Config fragment
-class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Config((site, here, up) => {
+class WithNMyCores(n: Int = 1) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
// Calculate the next available hart ID (since hart ID cannot be duplicated)
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
// Create TileAttachParams for every core to be instantiated
(0 until n).map { i =>
MyTileAttachParams(
- tileParams = MyTileParams(hartId = i + idOffset),
+ tileParams = MyTileParams(tileId = i + idOffset),
crossingParams = RocketCrossingParams()
)
} ++ prev
@@ -245,5 +247,6 @@ class WithNMyCores(n: Int = 1, overrideIdOffset: Option[Int] = None) extends Con
case SystemBusKey => up(SystemBusKey, site).copy(beatBytes = 8)
// The # of instruction bits. Use maximum # of bits if your core supports both 32 and 64 bits.
case XLen => 64
+ case NumTiles => up(NumTiles) + n
})
// DOC include end: Config fragment
diff --git a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
index 01d72d24..df2ec35a 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/GenericFIR.scala
@@ -199,12 +199,13 @@ class TLGenericFIRChain[T<:Data:Ring] (genIn: T, genOut: T, coeffs: => Seq[T], p
trait CanHavePeripheryStreamingFIR extends BaseSubsystem {
val streamingFIR = p(GenericFIRKey) match {
case Some(params) => {
- val streamingFIR = LazyModule(new TLGenericFIRChain(
+ val domain = pbus.generateSynchronousDomain.suggestName("fir_domain")
+ val streamingFIR = domain { LazyModule(new TLGenericFIRChain(
genIn = FixedPoint(8.W, 3.BP),
genOut = FixedPoint(8.W, 3.BP),
coeffs = Seq(1.U.asFixedPoint(0.BP), 2.U.asFixedPoint(0.BP), 3.U.asFixedPoint(0.BP)),
- params = params))
- pbus.coupleTo("streamingFIR") { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+ params = params)) }
+ pbus.coupleTo("streamingFIR") { domain { streamingFIR.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) } := _ }
Some(streamingFIR)
}
case None => None
diff --git a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
index 45e05fc2..a2259ab1 100644
--- a/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
+++ b/generators/chipyard/src/main/scala/example/dsptools/StreamingPassthrough.scala
@@ -131,8 +131,9 @@ class TLStreamingPassthroughChain[T<:Data:Ring](params: StreamingPassthroughPara
trait CanHavePeripheryStreamingPassthrough { this: BaseSubsystem =>
val passthrough = p(StreamingPassthroughKey) match {
case Some(params) => {
- val streamingPassthroughChain = LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W)))
- pbus.coupleTo("streamingPassthrough") { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes) := _ }
+ val domain = pbus.generateSynchronousDomain.suggestName("streaming_passthrough_domain")
+ val streamingPassthroughChain = domain { LazyModule(new TLStreamingPassthroughChain(params, UInt(32.W))) }
+ pbus.coupleTo("streamingPassthrough") { domain { streamingPassthroughChain.mem.get := TLFIFOFixer() := TLFragmenter(pbus.beatBytes, pbus.blockBytes)} := _ }
Some(streamingPassthroughChain)
}
case None => None
diff --git a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
index 7695be70..309ec004 100644
--- a/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
+++ b/generators/chipyard/src/main/scala/iobinders/IOBinders.scala
@@ -1,7 +1,8 @@
package chipyard.iobinders
import chisel3._
-import chisel3.experimental.{Analog, IO, DataMirror}
+import chisel3.reflect.DataMirror
+import chisel3.experimental.Analog
import org.chipsalliance.cde.config._
import freechips.rocketchip.diplomacy._
@@ -28,7 +29,7 @@ import testchipip.spi.{SPIChipIO}
import testchipip.boot.{CanHavePeripheryCustomBootPin}
import testchipip.util.{ClockedIO}
import testchipip.iceblk.{CanHavePeripheryBlockDevice, BlockDeviceKey, BlockDeviceIO}
-import testchipip.cosim.{CanHaveTraceIOModuleImp, TraceOutputTop, SpikeCosimConfig}
+import testchipip.cosim.{CanHaveTraceIO, TraceOutputTop, SpikeCosimConfig}
import testchipip.tsi.{CanHavePeripheryUARTTSI, UARTTSIIO}
import icenet.{CanHavePeripheryIceNIC, SimNetwork, NicLoopback, NICKey, NICIOvonly}
import chipyard.{CanHaveMasterTLMemPort, ChipyardSystem, ChipyardSystemModule}
@@ -284,7 +285,9 @@ class JTAGChipIO extends Bundle {
val TDO = Output(Bool())
}
-class WithDebugIOCells extends OverrideLazyIOBinder({
+// WARNING: Don't disable syncReset unless you are trying to
+// get around bugs in RTL simulators
+class WithDebugIOCells(syncReset: Boolean = true) extends OverrideLazyIOBinder({
(system: HasPeripheryDebug) => {
implicit val p = GetSystemParameters(system)
val tlbus = system.asInstanceOf[BaseSubsystem].locateTLBusWrapper(p(ExportDebug).slaveWhere)
@@ -308,7 +311,7 @@ class WithDebugIOCells extends OverrideLazyIOBinder({
d.disableDebug.foreach { d => d := false.B }
// Drive JTAG on-chip IOs
d.systemjtag.map { j =>
- j.reset := ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool)
+ j.reset := (if (syncReset) ResetCatchAndSync(j.jtag.TCK, clockBundle.reset.asBool) else clockBundle.reset.asBool)
j.mfr_id := p(JtagDTMKey).idcodeManufId.U(11.W)
j.part_number := p(JtagDTMKey).idcodePartNum.U(16.W)
j.version := p(JtagDTMKey).idcodeVersion.U(4.W)
@@ -454,14 +457,14 @@ class WithTraceGenSuccessPunchthrough extends OverrideIOBinder({
}
})
-class WithTraceIOPunchthrough extends OverrideIOBinder({
- (system: CanHaveTraceIOModuleImp) => {
+class WithTraceIOPunchthrough extends OverrideLazyIOBinder({
+ (system: CanHaveTraceIO) => InModuleBody {
val ports: Option[TracePort] = system.traceIO.map { t =>
val trace = IO(DataMirror.internal.chiselTypeClone[TraceOutputTop](t)).suggestName("trace")
trace <> t
val p = GetSystemParameters(system)
- val chipyardSystem = system.asInstanceOf[ChipyardSystemModule[_]].outer.asInstanceOf[ChipyardSystem]
- val tiles = chipyardSystem.tiles
+ val chipyardSystem = system.asInstanceOf[ChipyardSystem]
+ val tiles = chipyardSystem.totalTiles.values
val cfg = SpikeCosimConfig(
isa = tiles.headOption.map(_.isaDTS).getOrElse(""),
vlen = tiles.headOption.map(_.tileParams.core.vLen).getOrElse(0),
@@ -510,8 +513,8 @@ class WithDontTouchPorts extends OverrideIOBinder({
})
class WithNMITiedOff extends ComposeIOBinder({
- (system: HasTilesModuleImp) => {
- system.nmi.flatten.foreach { nmi =>
+ (system: HasHierarchicalElementsRootContextModuleImp) => {
+ system.nmi.foreach { nmi =>
nmi.rnmi := false.B
nmi.rnmi_interrupt_vector := 0.U
nmi.rnmi_exception_vector := 0.U
diff --git a/generators/chipyard/src/main/scala/iobinders/Ports.scala b/generators/chipyard/src/main/scala/iobinders/Ports.scala
index feb7bccb..627693aa 100644
--- a/generators/chipyard/src/main/scala/iobinders/Ports.scala
+++ b/generators/chipyard/src/main/scala/iobinders/Ports.scala
@@ -91,6 +91,9 @@ case class CustomBootPort (val getIO: () => Bool)
case class ClockPort (val getIO: () => Clock, val freqMHz: Double)
extends Port[Clock]
+case class ClockTapPort (val getIO: () => Clock)
+ extends Port[Clock]
+
case class ResetPort (val getIO: () => AsyncReset)
extends Port[Reset]
diff --git a/generators/constellation b/generators/constellation
index 3632183f..81f005ff 160000
--- a/generators/constellation
+++ b/generators/constellation
@@ -1 +1 @@
-Subproject commit 3632183fd1171d00c7f78b32c305841d231031b7
+Subproject commit 81f005ffeac998ebf0619e0bd7f0d212d68a82c5
diff --git a/generators/cva6 b/generators/cva6
index 46323fcd..9d1c1068 160000
--- a/generators/cva6
+++ b/generators/cva6
@@ -1 +1 @@
-Subproject commit 46323fcd7407544c751b353f52e356eb8f33e9d1
+Subproject commit 9d1c106834824ddb8052b7f60574b2b544b40395
diff --git a/generators/fft-generator b/generators/fft-generator
index 811951b4..4e7e6cbb 160000
--- a/generators/fft-generator
+++ b/generators/fft-generator
@@ -1 +1 @@
-Subproject commit 811951b44a113f87710a6abaae4582120c1194ba
+Subproject commit 4e7e6cbbbc6ed96d27dbaeb2413764cd446c50b3
diff --git a/generators/firechip/src/main/scala/FireSim.scala b/generators/firechip/src/main/scala/FireSim.scala
index 4cca7557..599788bc 100644
--- a/generators/firechip/src/main/scala/FireSim.scala
+++ b/generators/firechip/src/main/scala/FireSim.scala
@@ -8,7 +8,7 @@ import chisel3._
import chisel3.experimental.{IO, annotate}
import freechips.rocketchip.prci._
-import freechips.rocketchip.subsystem.{BaseSubsystem, SubsystemDriveAsyncClockGroupsKey, HasTiles}
+import freechips.rocketchip.subsystem._
import org.chipsalliance.cde.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, InModuleBody, ValName}
import freechips.rocketchip.util.{ResetCatchAndSync, RecordMap}
@@ -103,8 +103,8 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
// FireSim ModelMultithreading
chiptops.foreach {
case c: ChipTop => c.lazySystem match {
- case ls: HasTiles => {
- if (p(FireSimMultiCycleRegFile)) ls.tiles.map {
+ case ls: InstantiatesHierarchicalElements => {
+ if (p(FireSimMultiCycleRegFile)) ls.totalTiles.values.map {
case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
r.module.fpuOpt.foreach(fpu => annotate(MemModelAnnotation(fpu.fpuImpl.regfile)))
@@ -120,7 +120,7 @@ class FireSim(implicit val p: Parameters) extends RawModule with HasHarnessInsta
}
case _ =>
}
- if (p(FireSimFAME5)) ls.tiles.map {
+ if (p(FireSimFAME5)) ls.totalTiles.values.map {
case b: BoomTile =>
annotate(EnableModelMultiThreadingAnnotation(b.module))
case r: RocketTile =>
diff --git a/generators/firechip/src/main/scala/TargetConfigs.scala b/generators/firechip/src/main/scala/TargetConfigs.scala
index eb092944..04bb26a4 100644
--- a/generators/firechip/src/main/scala/TargetConfigs.scala
+++ b/generators/firechip/src/main/scala/TargetConfigs.scala
@@ -85,6 +85,7 @@ class WithMinimalFireSimDesignTweaks extends Config(
new chipyard.harness.WithHarnessBinderClockFreqMHz(1000.0) ++
new chipyard.harness.WithClockFromHarness ++
new chipyard.harness.WithResetFromHarness ++
+ new chipyard.config.WithNoClockTap ++
new chipyard.clocking.WithPassthroughClockGenerator ++
// Required*: When using FireSim-as-top to provide a correct path to the target bootrom source
new WithBootROM ++
@@ -99,6 +100,8 @@ class WithMinimalFireSimDesignTweaks extends Config(
// Non-frequency tweaks that are generally applied to all firesim configs
class WithFireSimDesignTweaks extends Config(
new WithMinimalFireSimDesignTweaks ++
+ // Required: Remove the debug clock tap, this breaks compilation of target-level sim in FireSim
+ new chipyard.config.WithNoClockTap ++
// Required: Bake in the default FASED memory model
new WithDefaultMemModel ++
// Optional: reduce the width of the Serial TL interface
@@ -122,6 +125,7 @@ class WithFireSimHighPerfClocking extends Config(
// This frequency selection matches FireSim's legacy selection and is required
// to support 200Gb NIC performance. You may select a smaller value.
new chipyard.config.WithPeripheryBusFrequency(3200.0) ++
+ new chipyard.config.WithControlBusFrequency(3200.0) ++
new chipyard.config.WithSystemBusFrequency(3200.0) ++
new chipyard.config.WithFrontBusFrequency(3200.0) ++
new chipyard.config.WithControlBusFrequency(3200.0) ++
@@ -142,6 +146,7 @@ class WithFireSimConfigTweaks extends Config(
new chipyard.config.WithSystemBusFrequency(1000.0) ++
new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithPeripheryBusFrequency(1000.0) ++
+ new chipyard.config.WithControlBusFrequency(1000.0) ++
new chipyard.config.WithMemoryBusFrequency(1000.0) ++
new chipyard.config.WithFrontBusFrequency(1000.0) ++
new WithFireSimDesignTweaks
diff --git a/generators/ibex b/generators/ibex
index 66ec6e56..c2174aba 160000
--- a/generators/ibex
+++ b/generators/ibex
@@ -1 +1 @@
-Subproject commit 66ec6e56ed69df4e4af5383128cf21adf88b08fc
+Subproject commit c2174aba4fb304c7565c248f2a673f7151be896b
diff --git a/generators/icenet b/generators/icenet
index 18e88b57..d6a471f2 160000
--- a/generators/icenet
+++ b/generators/icenet
@@ -1 +1 @@
-Subproject commit 18e88b5779ffdd7d75ca62cf9909f0ffc6fda95b
+Subproject commit d6a471f2187c0671eea6567c7ba29e86e830e8d4
diff --git a/generators/nvdla b/generators/nvdla
index 730fad43..95697452 160000
--- a/generators/nvdla
+++ b/generators/nvdla
@@ -1 +1 @@
-Subproject commit 730fad4360e67b14b1a4656ac58aaa40cfd4fe6b
+Subproject commit 95697452e51ad56230a6e631bb02b3351c4293c6
diff --git a/generators/riscv-sodor b/generators/riscv-sodor
index c1c809eb..bbfc3c35 160000
--- a/generators/riscv-sodor
+++ b/generators/riscv-sodor
@@ -1 +1 @@
-Subproject commit c1c809ebd5c9a76cd60d8c3169cea4bf4b2fa8fd
+Subproject commit bbfc3c35100329386314c49b62b49a7f42f65e87
diff --git a/generators/rocket-chip b/generators/rocket-chip
index 50adbdb3..749a3eae 160000
--- a/generators/rocket-chip
+++ b/generators/rocket-chip
@@ -1 +1 @@
-Subproject commit 50adbdb3e4e18c2b3de57693323f4174b60f9767
+Subproject commit 749a3eae9678bc70b029c5b9091fae33fad539c4
diff --git a/generators/rocket-chip-blocks b/generators/rocket-chip-blocks
new file mode 160000
index 00000000..212c7b07
--- /dev/null
+++ b/generators/rocket-chip-blocks
@@ -0,0 +1 @@
+Subproject commit 212c7b070bc7132f31a26deec6b2bde9e0b1b612
diff --git a/generators/rocket-chip-inclusive-cache b/generators/rocket-chip-inclusive-cache
new file mode 160000
index 00000000..1332d226
--- /dev/null
+++ b/generators/rocket-chip-inclusive-cache
@@ -0,0 +1 @@
+Subproject commit 1332d2268ae01b2b311966d53a3ee0d930e83f07
diff --git a/generators/shuttle b/generators/shuttle
index e628836c..fd325d43 160000
--- a/generators/shuttle
+++ b/generators/shuttle
@@ -1 +1 @@
-Subproject commit e628836c3c4bfe29927cd9e1473801fab33dee6c
+Subproject commit fd325d43a162378dc1984e87297e6d710167db79
diff --git a/generators/sifive-blocks b/generators/sifive-blocks
deleted file mode 160000
index 5edd72e7..00000000
--- a/generators/sifive-blocks
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 5edd72e793ccb534b1395d0d8c1831754fd72fec
diff --git a/generators/sifive-cache b/generators/sifive-cache
deleted file mode 160000
index 51d400bd..00000000
--- a/generators/sifive-cache
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit 51d400bd32131e8914c6713bfb71bef690f2fe70
diff --git a/generators/testchipip b/generators/testchipip
index 063dc011..e844c51a 160000
--- a/generators/testchipip
+++ b/generators/testchipip
@@ -1 +1 @@
-Subproject commit 063dc011cf8767f96ffb8a3d42462001cc728c9d
+Subproject commit e844c51a084aebd89968166bab421dda87a1e693
diff --git a/generators/tracegen/src/main/scala/Configs.scala b/generators/tracegen/src/main/scala/Configs.scala
index 5d4f0211..f51052c5 100644
--- a/generators/tracegen/src/main/scala/Configs.scala
+++ b/generators/tracegen/src/main/scala/Configs.scala
@@ -13,19 +13,18 @@ import scala.math.{max, min}
class WithTraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
TraceGenTileAttachParams(
tileParams = TraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -48,23 +47,23 @@ class WithTraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
class WithBoomTraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
BoomTraceGenTileAttachParams(
tileParams = BoomTraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -84,24 +83,24 @@ class WithBoomTraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
class WithL2TraceGen(
n: Int = 2,
- overrideIdOffset: Option[Int] = None,
overrideMemOffset: Option[BigInt] = None)(
params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
nReqs: Int = 8192
) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => {
val prev = up(TilesLocated(InSubsystem), site)
- val idOffset = overrideIdOffset.getOrElse(prev.size)
+ val idOffset = up(NumTiles)
val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
params.zipWithIndex.map { case (dcp, i) =>
TraceGenTileAttachParams(
tileParams = TraceGenParams(
- hartId = i + idOffset,
+ tileId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
@@ -126,4 +125,5 @@ class WithL2TraceGen(
)
} ++ prev
}
+ case NumTiles => up(NumTiles) + n
})
diff --git a/generators/tracegen/src/main/scala/System.scala b/generators/tracegen/src/main/scala/System.scala
index 2a0ba3d5..488054d3 100644
--- a/generators/tracegen/src/main/scala/System.scala
+++ b/generators/tracegen/src/main/scala/System.scala
@@ -9,15 +9,28 @@ import freechips.rocketchip.subsystem._
import boom.lsu.BoomTraceGenTile
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
- with HasTiles
+ with InstantiatesHierarchicalElements
+ with HasTileNotificationSinks
+ with HasTileInputConstants
+ with HasHierarchicalElementsRootContext
+ with HasHierarchicalElements
with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil
- val tileStatusNodes = tiles.collect {
+
+ val tileStatusNodes = totalTiles.values.toSeq.collect {
case t: GroundTestTile => t.statusNode.makeSink()
case t: BoomTraceGenTile => t.statusNode.makeSink()
}
- lazy val debugNode = IntSyncXbar() := NullIntSyncSource()
+
+ lazy val fakeClockDomain = sbus.generateSynchronousDomain
+
+ lazy val clintOpt = None
+ lazy val debugOpt = None
+ lazy val plicOpt = None
+ lazy val clintDomainOpt = Some(fakeClockDomain)
+ lazy val plicDomainOpt = Some(fakeClockDomain)
+
override lazy val module = new TraceGenSystemModuleImp(this)
}
diff --git a/scripts/build-setup.sh b/scripts/build-setup.sh
index d3a66ca6..a55b10fd 100755
--- a/scripts/build-setup.sh
+++ b/scripts/build-setup.sh
@@ -38,12 +38,20 @@ usage() {
echo " --help -h : Display this message"
echo " --force -f : Skip all prompts and checks"
- echo " --skip-validate : DEPRECATED: Same functionality as --force"
echo " --verbose -v : Verbose printout"
echo " --use-unpinned-deps -ud : Use unpinned conda environment"
echo " --skip -s N : Skip step N in the list above. Use multiple times to skip multiple steps ('-s N -s M ...')."
+ echo " --skip-conda : Skip Conda initialization (step 1)"
+ echo " --skip-submodules : Skip submodule initialization (step 2)"
+ echo " --skip-toolchain : Skip toolchain collateral (step 3)"
+ echo " --skip-ctags : Skip ctags (step 4)"
+ echo " --skip-precompile : Skip precompiling sources (steps 5/7)"
+ echo " --skip-firesim : Skip Firesim initialization (steps 6/7)"
+ echo " --skip-marshal : Skip firemarshal initialization (steps 8/9)"
+ echo " --skip-circt : Skip CIRCT install (step 10)"
+ echo " --skip-clean : Skip repository clean-up (step 11)"
exit "$1"
}
@@ -73,6 +81,24 @@ do
--skip | -s)
shift
SKIP_LIST+=(${1}) ;;
+ --skip-conda)
+ SKIP_LIST+=(1) ;;
+ --skip-submodules)
+ SKIP_LIST+=(2) ;;
+ --skip-toolchain)
+ SKIP_LIST+=(3) ;;
+ --skip-ctags)
+ SKIP_LIST+=(4) ;;
+ --skip-precompile)
+ SKIP_LIST+=(5 6) ;;
+ --skip-firesim)
+ SKIP_LIST+=(6 7) ;;
+ --skip-marshal)
+ SKIP_LIST+=(8 9) ;;
+ --skip-circt)
+ SKIP_LIST+=(10) ;;
+ --skip-clean)
+ SKIP_LIST+=(11) ;;
* )
error "invalid option $1"
usage 1 ;;
diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch
index e47fbbf6..b64d7a43 100644
--- a/scripts/tutorial-patches/build.sbt.patch
+++ b/scripts/tutorial-patches/build.sbt.patch
@@ -5,7 +5,7 @@ index c3be6161..2a6d7160 100644
@@ -147,7 +147,7 @@ lazy val testchipip = (project in file("generators/testchipip"))
lazy val chipyard = (project in file("generators/chipyard"))
- .dependsOn(testchipip, rocketchip, boom, hwacha, sifive_blocks, sifive_cache, iocell,
+ .dependsOn(testchipip, rocketchip, boom, hwacha, rocketchip_blocks, rocketchip_inclusive_cache, iocell,
- sha3, // On separate line to allow for cleaner tutorial-setup patches
+ //sha3, // On separate line to allow for cleaner tutorial-setup patches
dsptools, rocket_dsp_utils,
diff --git a/scripts/uniquify-module-names.py b/scripts/uniquify-module-names.py
index 237054f2..0ddea49f 100755
--- a/scripts/uniquify-module-names.py
+++ b/scripts/uniquify-module-names.py
@@ -21,6 +21,7 @@ parser.add_argument("--gcpath", type=str, required=True, help="Path to gen-colla
args = parser.parse_args()
MODEL_SFX=args.model + "_UNIQUIFIED"
+SED=os.environ.get("SED", "sed")
def bash(cmd):
@@ -109,7 +110,7 @@ def generate_copy(c, sfx):
new_file = os.path.join(args.gcpath, new_file)
shutil.copy(cur_file, new_file)
- bash(f"sed -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
+ bash(f"{SED} -i 's/module\( \+\){cur_name}/module\\1{new_name}/' {new_file}")
return new_file
def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
@@ -136,7 +137,7 @@ def bfs_uniquify_modules(tree, common_fnames, verilog_module_filename):
new_file = generate_copy(cur_file, MODEL_SFX)
if parent is not None and ((parent, mod) not in updated_submodule):
parent_file = os.path.join(args.gcpath, verilog_module_filename[parent])
- bash(f"sed -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
+ bash(f"{SED} -i 's/\( \*\){mod}\( \+\)/\\1{mod}_{MODEL_SFX}\\2/' {parent_file}")
updated_submodule.add((parent, mod))
# add the uniquified module to the verilog_modul_filename dict
diff --git a/sims/firesim b/sims/firesim
index c113e2d6..d2501ec7 160000
--- a/sims/firesim
+++ b/sims/firesim
@@ -1 +1 @@
-Subproject commit c113e2d6001080749b20c5a60b67eb338267a823
+Subproject commit d2501ec790c3df9094cc729c33074b641c515b03
diff --git a/software/baremetal-ide b/software/baremetal-ide
new file mode 160000
index 00000000..f488090a
--- /dev/null
+++ b/software/baremetal-ide
@@ -0,0 +1 @@
+Subproject commit f488090a7f37da43610bd5017ee401526bf40fb2
diff --git a/variables.mk b/variables.mk
index 65f493d2..fc2fc127 100644
--- a/variables.mk
+++ b/variables.mk
@@ -29,8 +29,7 @@ HELP_SIMULATION_VARIABLES = \
" LOADMEM = riscv elf binary that should be loaded directly into simulated DRAM. LOADMEM=1 will load the BINARY elf" \
" LOADARCH = path to a architectural checkpoint directory that should end in .loadarch/, for restoring from a checkpoint" \
" VERBOSE_FLAGS = flags used when doing verbose simulation [$(VERBOSE_FLAGS)]" \
-" timeout_cycles = number of clock cycles before simulator times out, defaults to 10000000" \
-" bmark_timeout_cycles = number of clock cycles before benchmark simulator times out, defaults to 100000000"
+" TIMEOUT_CYCLES = number of clock cycles before simulator times out, defaults to 10000000"
# include default simulation rules
HELP_COMMANDS = \
@@ -275,7 +274,7 @@ PERMISSIVE_ON=+permissive
PERMISSIVE_OFF=+permissive-off
BINARY ?=
BINARIES ?=
-override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(timeout_cycles)
+override SIM_FLAGS += +dramsim +dramsim_ini_dir=$(TESTCHIP_DIR)/src/main/resources/dramsim2_ini +max-cycles=$(TIMEOUT_CYCLES)
VERBOSE_FLAGS ?= +verbose
# get_out_name is a function, 1st argument is the binary
get_out_name = $(subst $() $(),_,$(notdir $(basename $(1))))
@@ -301,7 +300,12 @@ build_dir =$(gen_dir)/$(long_name)
GEN_COLLATERAL_DIR ?=$(build_dir)/gen-collateral
#########################################################################################
-# assembly/benchmark variables
+# simulation variables
#########################################################################################
-timeout_cycles = 10000000
-bmark_timeout_cycles = 100000000
+TIMEOUT_CYCLES = 10000000
+
+# legacy timeout_cycles handling
+timeout_cycles ?=
+ifneq ($(timeout_cycles),)
+TIMEOUT_CYCLES=$(timeout_cycles)
+endif
diff --git a/vlsi/power.mk b/vlsi/power.mk
index ff1c1729..c006d338 100644
--- a/vlsi/power.mk
+++ b/vlsi/power.mk
@@ -23,7 +23,7 @@ endif
endif
echo " start_times: ['0ns']" >> $@
echo " end_times: [" >> $@
- echo " '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
+ echo " '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
echo " ]" >> $@
$(POWER_RTL_CONF): $(VLSI_RTL)
diff --git a/vlsi/sim.mk b/vlsi/sim.mk
index 1da6f0bc..f5ff85ff 100644
--- a/vlsi/sim.mk
+++ b/vlsi/sim.mk
@@ -64,7 +64,7 @@ endif
echo " execution_flags_meta: 'append'" >> $@
echo " saif.mode: 'time'" >> $@
echo " saif.start_time: '0ns'" >> $@
- echo " saif.end_time: '`bc <<< $(timeout_cycles)*$(CLOCK_PERIOD)`ns'" >> $@
+ echo " saif.end_time: '`bc <<< $(TIMEOUT_CYCLES)*$(CLOCK_PERIOD)`ns'" >> $@
ifndef USE_VPD
echo " options:" >> $@
echo ' - "-kdb"' >> $@