Merge remote-tracking branch 'origin/main' into symmetric_sertl

2024-01-11 11:43:24 -08:00
parent 96ffc8f0a1 8073ecb1e8
commit 45d74f6db2
84 changed files with 411 additions and 271 deletions
--- a/fpga/src/main/scala/arty100t/Configs.scala
+++ b/fpga/src/main/scala/arty100t/Configs.scala
@@ -18,7 +18,7 @@ import chipyard.{BuildSystem}

 // don't use FPGAShell's DesignKey
 class WithNoDesignKey extends Config((site, here, up) => {
-  case DesignKey => (p: Parameters) => new SimpleLazyModule()(p)
+  case DesignKey => (p: Parameters) => new SimpleLazyRawModule()(p)
 })

 // By default, this uses the on-board USB-UART for the TSI-over-UART link