Fix comment in ChipConfigs

generators/chipyard/src/main/scala/config/ChipConfigs.scala

@@ -31,7 +31,7 @@ class ChipLikeRocketConfig extends Config(
   //==================================
   // Set up buses
   //==================================
-  new testchipip.WithOffchipBusManager(MBUS) ++
+  new testchipip.WithOffchipBusClient(MBUS) ++
   new testchipip.WithOffchipBus ++
 
   //==================================
@@ -65,8 +65,8 @@ class ChipBringupHostConfig extends Config(
   //============================
   // Setup bus topology on the bringup system
   //============================
-  new testchipip.WithOffchipBusClient(SBUS,                                   // offchip bus hans off the SBUS
-    blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accesses directly through this system
+  new testchipip.WithOffchipBusClient(SBUS,                                    // offchip bus hangs off the SBUS
+    blockRange = AddressSet.misaligned(0x80000000L, (BigInt(1) << 30) * 4)) ++ // offchip bus should not see the main memory of the testchip, since that can be accessed directly
   new testchipip.WithOffchipBus ++                                             // offchip bus
 
   //=============================

generators/chipyard/src/main/scala/config/PeripheralDeviceConfigs.scala

@@ -2,6 +2,7 @@ package chipyard
 
 import org.chipsalliance.cde.config.{Config}
 import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
+import freechips.rocketchip.subsystem.{MBUS}
 
 // ---------------------------------------------------------
 // Configs which add non-default peripheral devices or ports
@@ -66,8 +67,8 @@ class dmiRocketConfig extends Config(
 
 class ManyPeripheralsRocketConfig extends Config(
   new testchipip.WithBlockDevice ++                          // add block-device module to peripherybus
-  new testchipip.WithOffchipBusClient(MBUS) ++
-  new testchipip.WithOffchipBus ++
+  new testchipip.WithOffchipBusClient(MBUS) ++               // OBUS provides backing memory to the MBUS
+  new testchipip.WithOffchipBus ++                           // OBUS must exist for serial-tl to master off-chip memory
   new testchipip.WithSerialTLMem(isMainMemory=true) ++       // set lbwif memory base to DRAM_BASE, use as main memory
   new chipyard.harness.WithSimSPIFlashModel(true) ++         // add the SPI flash model in the harness (read-only)
   new chipyard.harness.WithSimBlockDevice ++                 // drive block-device IOs with SimBlockDevice