96 lines
5.2 KiB
Scala
96 lines
5.2 KiB
Scala
package chipyard
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import org.chipsalliance.cde.config.{Config}
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import freechips.rocketchip.diplomacy.{AsynchronousCrossing}
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import freechips.rocketchip.subsystem.{MBUS}
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// ---------------------------------------------------------
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// Configs which add non-default peripheral devices or ports
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// ---------------------------------------------------------
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class LargeSPIFlashROMRocketConfig extends Config(
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new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
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new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class SmallSPIFlashRocketConfig extends Config(
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new chipyard.harness.WithSimSPIFlashModel(false) ++ // add the SPI flash model in the harness (writeable)
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new chipyard.config.WithSPIFlash(0x100000) ++ // add the SPI flash controller (1 MiB)
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class SimBlockDeviceRocketConfig extends Config(
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new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
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new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class BlockDeviceModelRocketConfig extends Config(
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new chipyard.harness.WithBlockDeviceModel ++ // drive block-device IOs with a BlockDeviceModel
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new testchipip.WithBlockDevice ++ // add block-device module to periphery bus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: GPIORocketConfig
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class GPIORocketConfig extends Config(
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new chipyard.config.WithGPIO ++ // add GPIOs to the peripherybus
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: GPIORocketConfig
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class LoopbackNICRocketConfig extends Config(
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new chipyard.harness.WithLoopbackNIC ++ // drive NIC IOs with loopback
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new icenet.WithIceNIC ++ // add an IceNIC
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class MMIORocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
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new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class LBWIFRocketConfig extends Config(
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new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include start: DmiRocket
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class dmiRocketConfig extends Config(
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new chipyard.harness.WithSerialTLTiedOff ++ // don't attach anything to serial-tl
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new chipyard.config.WithDMIDTM ++ // have debug module expose a clocked DMI port
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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// DOC include end: DmiRocket
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class ManyPeripheralsRocketConfig extends Config(
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new testchipip.WithBlockDevice ++ // add block-device module to peripherybus
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new testchipip.WithOffchipBusClient(MBUS) ++ // OBUS provides backing memory to the MBUS
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new testchipip.WithOffchipBus ++ // OBUS must exist for serial-tl to master off-chip memory
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new testchipip.WithSerialTLMem(isMainMemory=true) ++ // set lbwif memory base to DRAM_BASE, use as main memory
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new chipyard.harness.WithSimSPIFlashModel(true) ++ // add the SPI flash model in the harness (read-only)
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new chipyard.harness.WithSimBlockDevice ++ // drive block-device IOs with SimBlockDevice
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new chipyard.config.WithSPIFlash ++ // add the SPI flash controller
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new freechips.rocketchip.subsystem.WithDefaultMMIOPort ++ // add default external master port
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new freechips.rocketchip.subsystem.WithDefaultSlavePort ++ // add default external slave port
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new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove AXI4 backing memory
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class QuadChannelRocketConfig extends Config(
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new freechips.rocketchip.subsystem.WithNMemoryChannels(4) ++ // 4 AXI4 channels
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++
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new chipyard.config.AbstractConfig)
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class UARTTSIRocketConfig extends Config(
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new chipyard.harness.WithSerialTLTiedOff ++
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new testchipip.WithUARTTSIClient ++
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new chipyard.config.WithMemoryBusFrequency(10) ++
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new chipyard.config.WithFrontBusFrequency(10) ++
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new chipyard.config.WithPeripheryBusFrequency(10) ++
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new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // single rocket-core
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new chipyard.config.AbstractConfig)
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