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Merge branch 'dev' of github.com:ucb-bar/chipyard into custom-core-doc

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This commit is contained in:
Zitao Fang
2020-06-28 21:26:09 -07:00
parent 34bc8da002 863e68ff30
commit 42f93ff32d
27 changed files with 465 additions and 551 deletions
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1
.gitignore vendored
View File

@@ -18,3 +18,4 @@ tags
*~ *~
env-riscv-tools.sh env-riscv-tools.sh
env-esp-tools.sh env-esp-tools.sh
.bloop/

38
common.mk
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@@ -34,13 +34,8 @@ lookup_srcs = $(shell find -L $(1)/ -name target -prune -o -iname "*.$(2)" -prin
SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell) SOURCE_DIRS = $(addprefix $(base_dir)/,generators sims/firesim/sim tools/barstools/iocell)
SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala) SCALA_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),scala)
VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v) VLOG_SOURCES = $(call lookup_srcs,$(SOURCE_DIRS),sv) $(call lookup_srcs,$(SOURCE_DIRS),v)
# This assumes no SBT meta-build sources
######################################################################################### SBT_SOURCES = $(call lookup_srcs,$(base_dir),sbt)
# rocket and testchipip classes
#########################################################################################
# NB: target/ lives under source ----V , due to how we're handling midas dependency injection
ROCKET_CLASSES ?= "$(ROCKETCHIP_DIR)/src/target/scala-$(SCALA_VERSION_MAJOR)/classes:$(ROCKETCHIP_DIR)/chisel3/target/scala-$(SCALA_VERSION_MAJOR)/*"
TESTCHIPIP_CLASSES ?= "$(TESTCHIP_DIR)/target/scala-$(SCALA_VERSION_MAJOR)/classes"
######################################################################################### #########################################################################################
# jar creation variables and rules # jar creation variables and rules
@@ -60,11 +55,19 @@ $(FIRRTL_TEST_JAR): $(call lookup_srcs,$(CHIPYARD_FIRRTL_DIR),scala)
cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@ cp -p $(CHIPYARD_FIRRTL_DIR)/utils/bin/firrtl-test.jar $@
touch $@ touch $@
#########################################################################################
# Bloop Project Definitions
#########################################################################################
$(BLOOP_CONFIG_DIR)/TIMESTAMP: $(SBT_SOURCES)
cd $(base_dir) && $(SBT) "project chipyardRoot" "bloopInstall"
touch $@
######################################################################################### #########################################################################################
# create list of simulation file inputs # create list of simulation file inputs
######################################################################################### #########################################################################################
$(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(sim_files): $(call lookup_srcs,$(base_dir)/generators/utilities/src/main/scala,scala) $(FIRRTL_JAR) $(SCALA_BUILDTOOL_DEPS)
cd $(base_dir) && $(SBT) "project utilities" "runMain utilities.GenerateSimFiles -td $(build_dir) -sim $(sim_name)" $(call run_scala_main,utilities,utilities.GenerateSimFiles,-td $(build_dir) -sim $(sim_name))
######################################################################################### #########################################################################################
# create firrtl file rule and variables # create firrtl file rule and variables
@@ -76,11 +79,11 @@ $(FIRRTL_FILE) $(ANNO_FILE): generator_temp
# AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile # AG: must re-elaborate if ariane sources have changed... otherwise just run firrtl compile
generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS) generator_temp: $(SCALA_SOURCES) $(sim_files) $(EXTRA_GENERATOR_REQS)
mkdir -p $(build_dir) mkdir -p $(build_dir)
cd $(base_dir) && $(SBT) "project $(SBT_PROJECT)" "runMain $(GENERATOR_PACKAGE).Generator \ $(call run_scala_main,$(SBT_PROJECT),$(GENERATOR_PACKAGE).Generator,\
--target-dir $(build_dir) \ --target-dir $(build_dir) \
--name $(long_name) \ --name $(long_name) \
--top-module $(MODEL_PACKAGE).$(MODEL) \ --top-module $(MODEL_PACKAGE).$(MODEL) \
--legacy-configs $(CONFIG_PACKAGE).$(CONFIG)" --legacy-configs $(CONFIG_PACKAGE).$(CONFIG))
.PHONY: firrtl .PHONY: firrtl
firrtl: $(FIRRTL_FILE) firrtl: $(FIRRTL_FILE)
@@ -101,7 +104,7 @@ $(TOP_TARGETS) $(HARNESS_TARGETS): firrtl_temp
@echo "" > /dev/null @echo "" > /dev/null
firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES) firrtl_temp: $(FIRRTL_FILE) $(ANNO_FILE) $(VLOG_SOURCES)
cd $(base_dir) && $(SBT) "project tapeout" "runMain barstools.tapeout.transforms.GenerateTopAndHarness -o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)" && touch $(sim_top_blackboxes) $(sim_harness_blackboxes) $(call run_scala_main,tapeout,barstools.tapeout.transforms.GenerateTopAndHarness,-o $(TOP_FILE) -tho $(HARNESS_FILE) -i $(FIRRTL_FILE) --syn-top $(TOP) --harness-top $(VLOG_MODEL) -faf $(ANNO_FILE) -tsaof $(TOP_ANNO) -tdf $(sim_top_blackboxes) -tsf $(TOP_FIR) -thaof $(HARNESS_ANNO) -hdf $(sim_harness_blackboxes) -thf $(HARNESS_FIR) $(REPL_SEQ_MEM) $(HARNESS_CONF_FLAGS) -td $(build_dir)) && touch $(sim_top_blackboxes) $(sim_harness_blackboxes)
# DOC include end: FirrtlCompiler # DOC include end: FirrtlCompiler
# This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs # This file is for simulation only. VLSI flows should replace this file with one containing hard SRAMs
@@ -111,7 +114,7 @@ $(TOP_SMEMS_FILE) $(TOP_SMEMS_FIR): top_macro_temp
@echo "" > /dev/null @echo "" > /dev/null
top_macro_temp: $(TOP_SMEMS_CONF) top_macro_temp: $(TOP_SMEMS_CONF)
cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE)" $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler,-n $(TOP_SMEMS_CONF) -v $(TOP_SMEMS_FILE) -f $(TOP_SMEMS_FIR) $(MACROCOMPILER_MODE))
HARNESS_MACROCOMPILER_MODE = --mode synflops HARNESS_MACROCOMPILER_MODE = --mode synflops
.INTERMEDIATE: harness_macro_temp .INTERMEDIATE: harness_macro_temp
@@ -119,7 +122,7 @@ $(HARNESS_SMEMS_FILE) $(HARNESS_SMEMS_FIR): harness_macro_temp
@echo "" > /dev/null @echo "" > /dev/null
harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp harness_macro_temp: $(HARNESS_SMEMS_CONF) | top_macro_temp
cd $(base_dir) && $(SBT) "project barstoolsMacros" "runMain barstools.macros.MacroCompiler -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE)" $(call run_scala_main,barstoolsMacros,barstools.macros.MacroCompiler, -n $(HARNESS_SMEMS_CONF) -v $(HARNESS_SMEMS_FILE) -f $(HARNESS_SMEMS_FIR) $(HARNESS_MACROCOMPILER_MODE))
######################################################################################## ########################################################################################
# remove duplicate files and headers in list of simulation file inputs # remove duplicate files and headers in list of simulation file inputs
@@ -185,3 +188,10 @@ dramsim_lib = $(dramsim_dir)/libdramsim.a
$(dramsim_lib): $(dramsim_lib):
$(MAKE) -C $(dramsim_dir) $(notdir $@) $(MAKE) -C $(dramsim_dir) $(notdir $@)
#########################################################################################
# Implicit rule handling
#########################################################################################
# Disable all suffix rules to improve Make performance on systems running older
# versions of Make
.SUFFIXES:

2
generators/ariane

Submodule generators/ariane updated: 651134f3c4...0ed9107485

2
generators/boom

Submodule generators/boom updated: d77c2c3ff6...859c60553b

86
generators/chipyard/src/main/scala/ConfigFragments.scala
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@@ -4,20 +4,23 @@ import chisel3._
import chisel3.util.{log2Up} import chisel3.util.{log2Up}
import freechips.rocketchip.config.{Field, Parameters, Config} import freechips.rocketchip.config.{Field, Parameters, Config}
import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, WithRoccExample, WithNMemoryChannels, WithNBigCores, WithRV32, CacheBlockBytes} import freechips.rocketchip.subsystem._
import freechips.rocketchip.diplomacy.{LazyModule, ValName} import freechips.rocketchip.diplomacy.{LazyModule, ValName}
import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.{Debug} import freechips.rocketchip.devices.debug.{Debug}
import freechips.rocketchip.tile.{XLen, BuildRoCC, TileKey, LazyRoCC, RocketTileParams, MaxHartIdBits} import freechips.rocketchip.groundtest.{GroundTestSubsystem}
import freechips.rocketchip.tile._
import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams} import freechips.rocketchip.rocket.{RocketCoreParams, MulDivParams, DCacheParams, ICacheParams}
import freechips.rocketchip.util.{AsyncResetReg} import freechips.rocketchip.util.{AsyncResetReg}
import boom.common.{BoomTilesKey}
import ariane.{ArianeTilesKey}
import testchipip._ import testchipip._
import tracegen.{TraceGenSystem}
import hwacha.{Hwacha} import hwacha.{Hwacha}
import boom.common.{BoomTileAttachParams}
import ariane.{ArianeTileAttachParams}
import sifive.blocks.devices.gpio._ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._ import sifive.blocks.devices.spi._
@@ -60,26 +63,17 @@ class WithSPIFlash(size: BigInt = 0x10000000) extends Config((site, here, up) =>
}) })
class WithL2TLBs(entries: Int) extends Config((site, here, up) => { class WithL2TLBs(entries: Int) extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy( case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
core = tile.core.copy(nL2TLBEntries = entries) case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
)) core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy( case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tile.core.copy(nL2TLBEntries = entries) core = tp.tileParams.core.copy(nL2TLBEntries = entries)))
)) case other => other
}
}) })
class WithTracegenSystem extends Config((site, here, up) => { class WithTracegenSystem extends Config((site, here, up) => {
case BuildSystem => (p: Parameters) => LazyModule(new tracegen.TraceGenSystem()(p)) case BuildSystem => (p: Parameters) => LazyModule(new TraceGenSystem()(p))
})
class WithRenumberHarts(rocketFirst: Boolean = false) extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site).zipWithIndex map { case (r, i) =>
r.copy(hartId = i + (if(rocketFirst) 0 else up(BoomTilesKey, site).length))
}
case BoomTilesKey => up(BoomTilesKey, site).zipWithIndex map { case (b, i) =>
b.copy(hartId = i + (if(rocketFirst) up(RocketTilesKey, site).length else 0))
}
case MaxHartIdBits => log2Up(up(BoomTilesKey, site).size + up(RocketTilesKey, site).size)
}) })
/** /**
@@ -107,7 +101,6 @@ class WithMultiRoCC extends Config((site, here, up) => {
*/ */
class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => { class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
case MultiRoCCKey => { case MultiRoCCKey => {
require(harts.max <= ((up(RocketTilesKey, site).length + up(BoomTilesKey, site).length) - 1))
up(MultiRoCCKey, site) ++ harts.distinct.map{ i => up(MultiRoCCKey, site) ++ harts.distinct.map{ i =>
(i -> Seq((p: Parameters) => { (i -> Seq((p: Parameters) => {
LazyModule(new Hwacha()(p)).suggestName("hwacha") LazyModule(new Hwacha()(p)).suggestName("hwacha")
@@ -117,38 +110,23 @@ class WithMultiRoCCHwacha(harts: Int*) extends Config((site, here, up) => {
}) })
/**
* Config fragment to add a small Rocket core to the system as a "control" core.
* Used as an example of a PMU core.
*/
class WithControlCore extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey, site) :+
RocketTileParams(
core = RocketCoreParams(
useVM = false,
fpu = None,
mulDiv = Some(MulDivParams(mulUnroll = 8))),
btb = None,
dcache = Some(DCacheParams(
rowBits = site(SystemBusKey).beatBits,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
nMSHRs = 0,
blockBytes = site(CacheBlockBytes))),
icache = Some(ICacheParams(
rowBits = site(SystemBusKey).beatBits,
nSets = 64,
nWays = 1,
nTLBEntries = 4,
blockBytes = site(CacheBlockBytes))),
hartId = up(RocketTilesKey, site).size + up(BoomTilesKey, site).size
)
case MaxHartIdBits => log2Up(up(RocketTilesKey, site).size + up(BoomTilesKey, site).size + 1)
})
class WithTraceIO extends Config((site, here, up) => { class WithTraceIO extends Config((site, here, up) => {
case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true)) case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case ArianeTilesKey => up(ArianeTilesKey) map (tile => tile.copy(trace = true)) case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
case tp: ArianeTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
trace = true))
case other => other
}
case TracePortKey => Some(TracePortParams()) case TracePortKey => Some(TracePortParams())
}) })
class WithNPerfCounters(n: Int = 29) extends Config((site, here, up) => {
case TilesLocated(InSubsystem) => up(TilesLocated(InSubsystem), site) map {
case tp: RocketTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case tp: BoomTileAttachParams => tp.copy(tileParams = tp.tileParams.copy(
core = tp.tileParams.core.copy(nPerfCounters = n)))
case other => other
}
})

4
generators/chipyard/src/main/scala/DigitalTop.scala
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@@ -12,7 +12,7 @@ import freechips.rocketchip.devices.tilelink._
// ------------------------------------ // ------------------------------------
// DOC include start: DigitalTop // DOC include start: DigitalTop
class DigitalTop(implicit p: Parameters) extends System class DigitalTop(implicit p: Parameters) extends ChipyardSystem
with testchipip.CanHaveTraceIO // Enables optionally adding trace IO with testchipip.CanHaveTraceIO // Enables optionally adding trace IO
with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad with testchipip.CanHaveBackingScratchpad // Enables optionally adding a backing scratchpad
with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device with testchipip.CanHavePeripheryBlockDevice // Enables optionally adding the block device
@@ -30,7 +30,7 @@ class DigitalTop(implicit p: Parameters) extends System
override lazy val module = new DigitalTopModule(this) override lazy val module = new DigitalTopModule(this)
} }
class DigitalTopModule[+L <: DigitalTop](l: L) extends SystemModule(l) class DigitalTopModule[+L <: DigitalTop](l: L) extends ChipyardSystemModule(l)
with testchipip.CanHaveTraceIOModuleImp with testchipip.CanHaveTraceIOModuleImp
with testchipip.CanHavePeripheryBlockDeviceModuleImp with testchipip.CanHavePeripheryBlockDeviceModuleImp
with testchipip.CanHavePeripherySerialModuleImp with testchipip.CanHavePeripherySerialModuleImp

11
generators/chipyard/src/main/scala/IOBinders.scala
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@@ -11,16 +11,17 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.{SimAXIMem} import freechips.rocketchip.system.{SimAXIMem}
import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters} import freechips.rocketchip.amba.axi4.{AXI4Bundle, AXI4SlaveNode, AXI4EdgeParameters}
import freechips.rocketchip.util._ import freechips.rocketchip.util._
import freechips.rocketchip.groundtest.{GroundTestSubsystemModuleImp, GroundTestSubsystem}
import sifive.blocks.devices.gpio._ import sifive.blocks.devices.gpio._
import sifive.blocks.devices.uart._ import sifive.blocks.devices.uart._
import sifive.blocks.devices.spi._ import sifive.blocks.devices.spi._
import tracegen.{TraceGenSystemModuleImp}
import barstools.iocell.chisel._ import barstools.iocell.chisel._
import testchipip._ import testchipip._
import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey} import icenet.{CanHavePeripheryIceNICModuleImp, SimNetwork, NicLoopback, NICKey}
import tracegen.{HasTraceGenTilesModuleImp}
import scala.reflect.{ClassTag} import scala.reflect.{ClassTag}
@@ -185,9 +186,9 @@ object AddIOCells {
} }
def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = { def axi4(io: Seq[AXI4Bundle], node: AXI4SlaveNode): Seq[(AXI4Bundle, AXI4EdgeParameters, Seq[IOCell])] = {
io.zip(node.in).map{ case (mem_axi4, (_, edge)) => { io.zip(node.in).zipWithIndex.map{ case ((mem_axi4, (_, edge)), i) => {
val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some("iocell_mem_axi4")) val (port, ios) = IOCell.generateIOFromSignal(mem_axi4, Some(s"iocell_mem_axi4_${i}"))
port.suggestName("mem_axi4") port.suggestName(s"mem_axi4_${i}")
(port, edge, ios) (port, edge, ios)
}} }}
} }
@@ -389,7 +390,7 @@ class WithSimSerial extends OverrideIOBinder({
}) })
class WithTraceGenSuccessBinder extends OverrideIOBinder({ class WithTraceGenSuccessBinder extends OverrideIOBinder({
(system: HasTraceGenTilesModuleImp) => { (system: TraceGenSystemModuleImp) => {
val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success")) val (successPort, ioCells) = IOCell.generateIOFromSignal(system.success, Some("iocell_success"))
successPort.suggestName("success") successPort.suggestName("success")
val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil } val harnessFn = (th: chipyard.TestHarness) => { when (successPort) { th.success := true.B }; Nil }

97
generators/chipyard/src/main/scala/Subsystem.scala
View File

@@ -10,7 +10,7 @@ import chisel3.internal.sourceinfo.{SourceInfo}
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.devices.tilelink._ import freechips.rocketchip.devices.tilelink._
import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp} import freechips.rocketchip.devices.debug.{HasPeripheryDebug, HasPeripheryDebugModuleImp, ExportDebug}
import freechips.rocketchip.diplomacy._ import freechips.rocketchip.diplomacy._
import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt} import freechips.rocketchip.diplomaticobjectmodel.model.{OMInterrupt}
import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree} import freechips.rocketchip.diplomaticobjectmodel.logicaltree.{RocketTileLogicalTreeNode, LogicalModuleTree}
@@ -21,93 +21,60 @@ import freechips.rocketchip.util._
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.amba.axi4._ import freechips.rocketchip.amba.axi4._
import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams} import boom.common.{BoomTile}
import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
import testchipip.{DromajoHelper}
trait HasChipyardTiles extends HasTiles import testchipip.{DromajoHelper, CanHavePeripherySerial, SerialKey}
with CanHavePeripheryPLIC
with CanHavePeripheryCLINT
with HasPeripheryDebug
{ this: BaseSubsystem =>
val module: HasChipyardTilesModuleImp
protected val rocketTileParams = p(RocketTilesKey) trait CanHaveHTIF { this: BaseSubsystem =>
protected val boomTileParams = p(BoomTilesKey) // Advertise HTIF if system can communicate with fesvr
protected val arianeTileParams = p(ArianeTilesKey) if (this match {
case _: CanHavePeripherySerial if p(SerialKey) => true
// crossing can either be per tile or global (aka only 1 crossing specified) case _: HasPeripheryDebug if p(ExportDebug).protocols.nonEmpty => true
private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size) case _ => false
private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size) }) {
private val arianeCrossings = perTileOrGlobalSetting(p(ArianeCrossingKey), arianeTileParams.size) ResourceBinding {
val htif = new Device {
val allTilesInfo = (rocketTileParams ++ boomTileParams ++ arianeTileParams) zip (rocketCrossings ++ boomCrossings ++ arianeCrossings) def describe(resources: ResourceBindings): Description = {
val compat = resources("compat").map(_.value)
// Make a tile and wire its nodes into the system, Description("htif", Map(
// according to the specified type of clock crossing. "compatible" -> compat))
// Note that we also inject new nodes into the tile itself,
// also based on the crossing type.
// This MUST be performed in order of hartid
// There is something weird with registering tile-local interrupt controllers to the CLINT.
// TODO: investigate why
val tiles = allTilesInfo.sortWith(_._1.hartId < _._1.hartId).map {
case (param, crossing) => {
val tile = param match {
case r: RocketTileParams => {
LazyModule(new RocketTile(r, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
}
case b: BoomTileParams => {
LazyModule(new BoomTile(b, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
}
case a: ArianeTileParams => {
LazyModule(new ArianeTile(a, crossing, PriorityMuxHartIdFromSeq(arianeTileParams), logicalTreeNode))
} }
} }
connectMasterPortsToSBus(tile, crossing) Resource(htif, "compat").bind(ResourceString("ucb,htif0"))
connectSlavePortsToCBus(tile, crossing)
connectInterrupts(tile, debugOpt, clintOpt, plicOpt)
tile
} }
} }
}
class ChipyardSubsystem(implicit p: Parameters) extends BaseSubsystem
with HasTiles
with CanHaveHTIF
{
def coreMonitorBundles = tiles.map { def coreMonitorBundles = tiles.map {
case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle case r: RocketTile => r.module.core.rocketImpl.coreMonitorBundle
case b: BoomTile => b.module.core.coreMonitorBundle case b: BoomTile => b.module.core.coreMonitorBundle
}.toList }.toList
override lazy val module = new ChipyardSubsystemModuleImp(this)
} }
trait HasChipyardTilesModuleImp extends HasTilesModuleImp
with HasPeripheryDebugModuleImp
{
val outer: HasChipyardTiles
}
class Subsystem(implicit p: Parameters) extends BaseSubsystem class ChipyardSubsystemModuleImp[+L <: ChipyardSubsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasChipyardTiles
{
override lazy val module = new SubsystemModuleImp(this)
def getOMInterruptDevice(resourceBindingsMap: ResourceBindingsMap): Seq[OMInterrupt] = Nil
}
class SubsystemModuleImp[+L <: Subsystem](_outer: L) extends BaseSubsystemModuleImp(_outer)
with HasResetVectorWire with HasResetVectorWire
with HasChipyardTilesModuleImp with HasTilesModuleImp
{ {
tile_inputs.zip(outer.hartIdList).foreach { case(wire, i) =>
wire.hartid := i.U for (i <- 0 until outer.tiles.size) {
val wire = tile_inputs(i)
wire.hartid := outer.hartIdList(i).U
wire.reset_vector := global_reset_vector wire.reset_vector := global_reset_vector
} }
// create file with boom params // create file with core params
ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n")) ElaborationArtefacts.add("""core.config""", outer.tiles.map(x => x.module.toString).mkString("\n"))
// Generate C header with relevant information for Dromajo // Generate C header with relevant information for Dromajo
// This is included in the `dromajo_params.h` header file // This is included in the `dromajo_params.h` header file
DromajoHelper.addArtefacts DromajoHelper.addArtefacts()
} }

6
generators/chipyard/src/main/scala/System.scala
View File

@@ -21,20 +21,20 @@ import freechips.rocketchip.util.{DontTouch}
/** /**
* Base top with periphery devices and ports, and a BOOM + Rocket subsystem * Base top with periphery devices and ports, and a BOOM + Rocket subsystem
*/ */
class System(implicit p: Parameters) extends Subsystem class ChipyardSystem(implicit p: Parameters) extends ChipyardSubsystem
with HasAsyncExtInterrupts with HasAsyncExtInterrupts
with CanHaveMasterAXI4MemPort with CanHaveMasterAXI4MemPort
with CanHaveMasterAXI4MMIOPort with CanHaveMasterAXI4MMIOPort
with CanHaveSlaveAXI4Port with CanHaveSlaveAXI4Port
with HasPeripheryBootROM with HasPeripheryBootROM
{ {
override lazy val module = new SystemModule(this) override lazy val module = new ChipyardSystemModule(this)
} }
/** /**
* Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem * Base top module implementation with periphery devices and ports, and a BOOM + Rocket subsystem
*/ */
class SystemModule[+L <: System](_outer: L) extends SubsystemModuleImp(_outer) class ChipyardSystemModule[+L <: ChipyardSystem](_outer: L) extends ChipyardSubsystemModuleImp(_outer)
with HasRTCModuleImp with HasRTCModuleImp
with HasExtInterruptsModuleImp with HasExtInterruptsModuleImp
with HasPeripheryBootROMModuleImp with HasPeripheryBootROMModuleImp

192
generators/chipyard/src/main/scala/TestSuites.scala
View File

@@ -2,13 +2,13 @@ package chipyard
import scala.collection.mutable.{LinkedHashSet} import scala.collection.mutable.{LinkedHashSet}
import freechips.rocketchip.subsystem.{RocketTilesKey} import freechips.rocketchip.subsystem._
import freechips.rocketchip.tile.{XLen} import freechips.rocketchip.tile.{XLen}
import freechips.rocketchip.config.{Parameters} import freechips.rocketchip.config.{Parameters}
import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite} import freechips.rocketchip.system.{TestGeneration, RegressionTestSuite, RocketTestSuite}
import boom.common.{BoomTilesKey} import boom.common.{BoomTileAttachParams}
import ariane.{ArianeTilesKey} import ariane.{ArianeTileAttachParams}
/** /**
* A set of pre-chosen regression tests * A set of pre-chosen regression tests
@@ -68,39 +68,43 @@ class TestSuiteHelper
*/ */
def addBoomTestSuites(implicit p: Parameters) = { def addBoomTestSuites(implicit p: Parameters) = {
val xlen = p(XLen) val xlen = p(XLen)
p(BoomTilesKey).find(_.hartId == 0).map { tileParams => p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
val coreParams = tileParams.core case tp: BoomTileAttachParams => {
val vm = coreParams.useVM val tileParams = tp.tileParams
val env = if (vm) List("p","v") else List("p") val coreParams = tileParams.core
coreParams.fpu foreach { case cfg => val vm = coreParams.useVM
if (xlen == 32) { val env = if (vm) List("p","v") else List("p")
addSuites(env.map(rv32uf)) coreParams.fpu foreach { case cfg =>
if (cfg.fLen >= 64) { if (xlen == 32) {
addSuites(env.map(rv32ud)) addSuites(env.map(rv32uf))
if (cfg.fLen >= 64) {
addSuites(env.map(rv32ud))
}
} else if (cfg.fLen >= 64) {
addSuites(env.map(rv64ud))
addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
} }
} else if (cfg.fLen >= 64) {
addSuites(env.map(rv64ud))
addSuites(env.map(rv64uf))
addSuite(rv32udBenchmarks)
} }
} if (coreParams.useAtomics) {
if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
if (tileParams.dcache.flatMap(_.scratch).isEmpty) { addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) } else {
} else { addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) }
} }
} if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) =
val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u)
else ((if (vm) rv32i else rv32pi), rv32u)
addSuites(rvi.map(_("p"))) addSuites(rvi.map(_("p")))
addSuites(rvu.map(_("p"))) addSuites(rvu.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks) addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
case _ =>
} }
} }
@@ -109,37 +113,41 @@ class TestSuiteHelper
*/ */
def addRocketTestSuites(implicit p: Parameters) = { def addRocketTestSuites(implicit p: Parameters) = {
val xlen = p(XLen) val xlen = p(XLen)
p(RocketTilesKey).find(_.hartId == 0).map { tileParams => p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
val coreParams = tileParams.core case tp: RocketTileAttachParams => {
val vm = coreParams.useVM val tileParams = tp.tileParams
val env = if (vm) List("p","v") else List("p") val coreParams = tileParams.core
coreParams.fpu foreach { case cfg => val vm = coreParams.useVM
if (xlen == 32) { val env = if (vm) List("p","v") else List("p")
addSuites(env.map(rv32uf)) coreParams.fpu foreach { case cfg =>
if (cfg.fLen >= 64) if (xlen == 32) {
addSuites(env.map(rv32ud)) addSuites(env.map(rv32uf))
} else { if (cfg.fLen >= 64)
addSuite(rv32udBenchmarks) addSuites(env.map(rv32ud))
addSuites(env.map(rv64uf)) } else {
if (cfg.fLen >= 64) addSuite(rv32udBenchmarks)
addSuites(env.map(rv64ud)) addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
addSuites(env.map(rv64ud))
}
} }
} if (coreParams.useAtomics) {
if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty)
if (tileParams.dcache.flatMap(_.scratch).isEmpty) addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else
else addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) }
} if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) =
val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u)
else ((if (vm) rv32i else rv32pi), rv32u)
addSuites(rvi.map(_("p"))) addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks) addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
case _ =>
} }
} }
@@ -148,37 +156,41 @@ class TestSuiteHelper
*/ */
def addArianeTestSuites(implicit p: Parameters) = { def addArianeTestSuites(implicit p: Parameters) = {
val xlen = p(XLen) val xlen = p(XLen)
p(ArianeTilesKey).find(_.hartId == 0).map { tileParams => p(TilesLocated(InSubsystem)).find(_.tileParams.hartId == 0).map {
val coreParams = tileParams.core case tp: ArianeTileAttachParams => {
val vm = coreParams.useVM val tileParams = tp.tileParams
val env = if (vm) List("p","v") else List("p") val coreParams = tileParams.core
coreParams.fpu foreach { case cfg => val vm = coreParams.useVM
if (xlen == 32) { val env = if (vm) List("p","v") else List("p")
addSuites(env.map(rv32uf)) coreParams.fpu foreach { case cfg =>
if (cfg.fLen >= 64) if (xlen == 32) {
addSuites(env.map(rv32ud)) addSuites(env.map(rv32uf))
} else { if (cfg.fLen >= 64)
addSuite(rv32udBenchmarks) addSuites(env.map(rv32ud))
addSuites(env.map(rv64uf)) } else {
if (cfg.fLen >= 64) addSuite(rv32udBenchmarks)
addSuites(env.map(rv64ud)) addSuites(env.map(rv64uf))
if (cfg.fLen >= 64)
addSuites(env.map(rv64ud))
}
} }
} if (coreParams.useAtomics) {
if (coreParams.useAtomics) { if (tileParams.dcache.flatMap(_.scratch).isEmpty)
if (tileParams.dcache.flatMap(_.scratch).isEmpty) addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
addSuites(env.map(if (xlen == 64) rv64ua else rv32ua)) else
else addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC)) }
} if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) =
val (rvi, rvu) = if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) else ((if (vm) rv32i else rv32pi), rv32u)
else ((if (vm) rv32i else rv32pi), rv32u)
addSuites(rvi.map(_("p"))) addSuites(rvi.map(_("p")))
addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env)))) addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
addSuite(benchmarks) addSuite(benchmarks)
addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames)) addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
}
case _ =>
} }
} }
} }

45
generators/chipyard/src/main/scala/config/BoomConfigs.scala
View File

@@ -20,8 +20,7 @@ class SmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
new boom.common.WithSmallBooms ++ // small boom config new boom.common.WithNSmallBooms(1) ++ // small boom config
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2
new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
@@ -39,8 +38,7 @@ class MediumBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMediumBooms ++ // medium boom config new boom.common.WithNMediumBooms(1) ++ // medium boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -58,8 +56,7 @@ class LargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++ // large boom config new boom.common.WithNLargeBooms(1) ++ // large boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -77,8 +74,7 @@ class MegaBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithMegaBooms ++ // mega boom config new boom.common.WithNMegaBooms(1) ++ // mega boom config
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -96,29 +92,7 @@ class DualSmallBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithSmallBooms ++ new boom.common.WithNSmallBooms(2) ++ // 2 boom cores
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
class SmallRV32BoomConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithoutBoomFPU ++ // no fp
new boom.common.WithBoomRV32 ++ // rv32 (32bit)
new boom.common.WithSmallBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -137,8 +111,7 @@ class HwachaLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++ new boom.common.WithNLargeBooms(1) ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -158,8 +131,7 @@ class LoopbackNICLargeBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithLargeBooms ++ new boom.common.WithNLargeBooms(1) ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
@@ -179,8 +151,7 @@ class DromajoBoomConfig extends Config(
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new boom.common.WithSmallBooms ++ new boom.common.WithNSmallBooms(1) ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)

70
generators/chipyard/src/main/scala/config/HeteroConfigs.scala
View File

@@ -16,9 +16,7 @@ class LargeBoomAndRocketConfig extends Config(
new chipyard.config.WithBootROM ++ // use default bootrom new chipyard.config.WithBootROM ++ // use default bootrom
new chipyard.config.WithUART ++ // add a UART new chipyard.config.WithUART ++ // add a UART
new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
new chipyard.config.WithRenumberHarts ++ // avoid hartid overlap new boom.common.WithNLargeBooms(1) ++ // single-core boom
new boom.common.WithLargeBooms ++ // 3-wide boom
new boom.common.WithNBoomCores(1) ++ // single-core boom
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
@@ -39,9 +37,7 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++ new chipyard.config.WithL2TLBs(1024) ++
new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts new hwacha.DefaultHwachaConfig ++ // add hwacha to all harts
new chipyard.config.WithRenumberHarts ++ new boom.common.WithNLargeBooms(1) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
@@ -50,28 +46,6 @@ class HwachaLargeBoomAndHwachaRocketConfig extends Config(
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.system.BaseConfig)
// DOC include end: BoomAndRocketWithHwacha // DOC include end: BoomAndRocketWithHwacha
class DualLargeBoomAndRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: DualBoomAndRocketOneHwacha // DOC include start: DualBoomAndRocketOneHwacha
class LargeBoomAndHwachaRocketConfig extends Config( class LargeBoomAndHwachaRocketConfig extends Config(
@@ -84,11 +58,9 @@ class LargeBoomAndHwachaRocketConfig extends Config(
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc new chipyard.config.WithMultiRoCC ++ // support heterogeneous rocc
new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-2 (rocket) new chipyard.config.WithMultiRoCCHwacha(1) ++ // put hwacha on hart-1 (rocket)
new chipyard.config.WithL2TLBs(1024) ++ new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithRenumberHarts ++ new boom.common.WithNLargeBooms(1) ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
@@ -99,30 +71,6 @@ class LargeBoomAndHwachaRocketConfig extends Config(
// DOC include end: DualBoomAndRocketOneHwacha // DOC include end: DualBoomAndRocketOneHwacha
class LargeBoomAndRV32RocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++
new chipyard.iobinders.WithTieOffInterrupts ++
new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTiedOffDebug ++
new chipyard.iobinders.WithSimSerial ++
new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithRenumberHarts ++
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++
new freechips.rocketchip.subsystem.WithRV32 ++ // set RocketTiles to be 32-bit
new freechips.rocketchip.subsystem.WithNBigCores(1) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig)
// DOC include start: DualBoomAndRocket // DOC include start: DualBoomAndRocket
class DualLargeBoomAndDualRocketConfig extends Config( class DualLargeBoomAndDualRocketConfig extends Config(
new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithUARTAdapter ++
@@ -134,9 +82,7 @@ class DualLargeBoomAndDualRocketConfig extends Config(
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
new chipyard.config.WithL2TLBs(1024) ++ new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithRenumberHarts ++ new boom.common.WithNLargeBooms(2) ++ // 2 boom cores
new boom.common.WithLargeBooms ++
new boom.common.WithNBoomCores(2) ++ // 2 boom cores
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
@@ -155,11 +101,9 @@ class LargeBoomAndRocketWithControlCoreConfig extends Config(
new testchipip.WithTSI ++ new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
new chipyard.config.WithControlCore ++ // add small control core to last hartid
new chipyard.config.WithL2TLBs(1024) ++ new chipyard.config.WithL2TLBs(1024) ++
new chipyard.config.WithRenumberHarts ++ new freechips.rocketchip.subsystem.WithNSmallCores(1) ++ // Add a small control core
new boom.common.WithLargeBooms ++ new boom.common.WithNLargeBooms(1) ++
new boom.common.WithNBoomCores(1) ++
new freechips.rocketchip.subsystem.WithNoMMIOPort ++ new freechips.rocketchip.subsystem.WithNoMMIOPort ++
new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithNoSlavePort ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++

20
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
View File

@@ -7,42 +7,42 @@ class TraceGenConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenConfig extends Config( class NonBlockingTraceGenConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class BoomTraceGenConfig extends Config( class BoomTraceGenConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithBoomTraceGen(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenL2Config extends Config( class NonBlockingTraceGenL2Config extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenL2RingConfig extends Config( class NonBlockingTraceGenL2RingConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
new chipyard.iobinders.WithTraceGenSuccessBinder ++ new chipyard.iobinders.WithTraceGenSuccessBinder ++
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithL2TraceGen(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new testchipip.WithRingSystemBus ++ new testchipip.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)

9
generators/chipyard/src/main/scala/config/TutorialConfigs.scala
View File

@@ -30,15 +30,13 @@ class TutorialStarterConfig extends Config(
// of the Top // of the Top
new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core new testchipip.WithTSI ++ // Add a TSI (Test Serial Interface) widget to bring-up the core
new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM new chipyard.config.WithBootROM ++ // Use the Chipyard BootROM
new chipyard.config.WithRenumberHarts ++ // WithRenumberHarts fixes hartids heterogeneous designs, if design is not heterogeneous, this is a no-op
new chipyard.config.WithUART ++ // Add a UART new chipyard.config.WithUART ++ // Add a UART
// CUSTOMIZE THE CORE // CUSTOMIZE THE CORE
// Uncomment out one (or multiple) of the lines below, and choose // Uncomment out one (or multiple) of the lines below, and choose
// how many cores you want. // how many cores you want.
// new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores // new freechips.rocketchip.subsystem.WithNBigCores(1) ++ // Specify we want some number of Rocket cores
// new boom.common.WithSmallBooms ++ // Specify all BOOM cores should be Small-sized (NOTE: other options are Medium/Large/Mega) // new boom.common.WithNSmallBooms(1) ++ // Specify we want some number of BOOM cores
// new boom.common.WithNBoomCores(1) ++ // Specify we want some number of BOOM cores
// CUSTOMIZE the L2 // CUSTOMIZE the L2
// Uncomment this line, and specify a size if you want to have a L2 // Uncomment this line, and specify a size if you want to have a L2
@@ -66,7 +64,6 @@ class TutorialMMIOConfig extends Config(
new testchipip.WithTSI ++ new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
// Attach either a TileLink or AXI4 version of GCD // Attach either a TileLink or AXI4 version of GCD
@@ -94,7 +91,6 @@ class TutorialSha3Config extends Config(
new testchipip.WithTSI ++ new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
// Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo // Uncomment this line once you added SHA3 to the build.sbt, and cloned the SHA3 repo
@@ -120,7 +116,6 @@ class TutorialSha3BlackBoxConfig extends Config(
new testchipip.WithTSI ++ new testchipip.WithTSI ++
new chipyard.config.WithBootROM ++ new chipyard.config.WithBootROM ++
new chipyard.config.WithRenumberHarts ++
new chipyard.config.WithUART ++ new chipyard.config.WithUART ++
// Uncomment these lines once SHA3 is integrated // Uncomment these lines once SHA3 is integrated

11
generators/firechip/src/main/scala/BridgeBinders.scala
View File

@@ -8,7 +8,7 @@ import chisel3.experimental.annotate
import freechips.rocketchip.config.{Field, Config, Parameters} import freechips.rocketchip.config.{Field, Config, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule} import freechips.rocketchip.diplomacy.{LazyModule}
import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp} import freechips.rocketchip.devices.debug.{Debug, HasPeripheryDebugModuleImp}
import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem} import freechips.rocketchip.subsystem.{CanHaveMasterAXI4MemPort, HasExtInterruptsModuleImp, BaseSubsystem, HasTilesModuleImp}
import freechips.rocketchip.tile.{RocketTile} import freechips.rocketchip.tile.{RocketTile}
import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp import sifive.blocks.devices.uart.HasPeripheryUARTModuleImp
import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp} import sifive.blocks.devices.gpio.{HasPeripheryGPIOModuleImp}
@@ -21,13 +21,12 @@ import midas.models.{FASEDBridge, AXI4EdgeSummary, CompleteConfig}
import midas.targetutils.{MemModelAnnotation} import midas.targetutils.{MemModelAnnotation}
import firesim.bridges._ import firesim.bridges._
import firesim.configs.MemModelKey import firesim.configs.MemModelKey
import tracegen.HasTraceGenTilesModuleImp import tracegen.{TraceGenSystemModuleImp}
import ariane.ArianeTile import ariane.ArianeTile
import boom.common.{BoomTile} import boom.common.{BoomTile}
import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder} import chipyard.iobinders.{IOBinders, OverrideIOBinder, ComposeIOBinder}
import chipyard.{HasChipyardTilesModuleImp}
import testchipip.{CanHaveTraceIOModuleImp} import testchipip.{CanHaveTraceIOModuleImp}
object MainMemoryConsts { object MainMemoryConsts {
@@ -88,12 +87,12 @@ class WithDromajoBridge extends ComposeIOBinder({
class WithTraceGenBridge extends OverrideIOBinder({ class WithTraceGenBridge extends OverrideIOBinder({
(system: HasTraceGenTilesModuleImp) => (system: TraceGenSystemModuleImp) =>
GroundTestBridge(system.clock, system.success)(system.p); Nil GroundTestBridge(system.clock, system.success)(system.p); Nil
}) })
class WithFireSimMultiCycleRegfile extends ComposeIOBinder({ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
(system: HasChipyardTilesModuleImp) => { (system: HasTilesModuleImp) => {
system.outer.tiles.map { system.outer.tiles.map {
case r: RocketTile => { case r: RocketTile => {
annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf)) annotate(MemModelAnnotation(r.module.core.rocketImpl.rf.rf))
@@ -110,7 +109,7 @@ class WithFireSimMultiCycleRegfile extends ComposeIOBinder({
case _ => Nil case _ => Nil
} }
} }
case a: ArianeTile => Nil case _ =>
} }
Nil Nil
} }

20
generators/firechip/src/main/scala/FireSimMulticlockPOC.scala
View File

@@ -9,11 +9,11 @@ import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, RationalCrossi
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
import freechips.rocketchip.util.{ResetCatchAndSync} import freechips.rocketchip.util.{ResetCatchAndSync}
import boom.common.{BoomTilesKey, BoomCrossingKey}
import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock} import midas.widgets.{Bridge, PeekPokeBridge, RationalClockBridge, RationalClock}
import firesim.configs._ import firesim.configs._
import boom.common.{WithRationalBoomTiles}
import chipyard.{BuildSystem, DigitalTop, DigitalTopModule} import chipyard.{BuildSystem, DigitalTop, DigitalTopModule}
import chipyard.config.ConfigValName._ import chipyard.config.ConfigValName._
import chipyard.iobinders.{IOBinders} import chipyard.iobinders.{IOBinders}
@@ -51,15 +51,13 @@ trait HasFireSimClockingImp extends HasAdditionalClocks {
} }
// Config Fragment // Config Fragment
class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config((site, here, up) => { class WithSingleRationalTileDomain(multiplier: Int, divisor: Int) extends Config(
case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor))) new WithRationalRocketTiles ++
case RocketCrossingKey => up(RocketCrossingKey, site) map { r => new WithRationalBoomTiles ++
r.copy(crossingType = RationalCrossing()) new Config((site, here, up) => {
} case FireSimClockKey => FireSimClockParameters(Seq(RationalClock("TileDomain", multiplier, divisor)))
case BoomCrossingKey => up(BoomCrossingKey, site) map { r => })
r.copy(crossingType = RationalCrossing()) )
}
})
class HalfRateUncore extends WithSingleRationalTileDomain(2,1) class HalfRateUncore extends WithSingleRationalTileDomain(2,1)

10
generators/firechip/src/main/scala/TargetConfigs.scala
View File

@@ -13,13 +13,11 @@ import freechips.rocketchip.subsystem._
import freechips.rocketchip.devices.tilelink.BootROMParams import freechips.rocketchip.devices.tilelink.BootROMParams
import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey} import freechips.rocketchip.devices.debug.{DebugModuleParams, DebugModuleKey}
import freechips.rocketchip.diplomacy.LazyModule import freechips.rocketchip.diplomacy.LazyModule
import boom.common.BoomTilesKey
import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams} import testchipip.{BlockDeviceKey, BlockDeviceConfig, SerialKey, TracePortKey, TracePortParams}
import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams} import sifive.blocks.devices.uart.{PeripheryUARTKey, UARTParams}
import scala.math.{min, max} import scala.math.{min, max}
import tracegen.TraceGenKey
import icenet._ import icenet._
import ariane.ArianeTilesKey
import testchipip.WithRingSystemBus import testchipip.WithRingSystemBus
import firesim.bridges._ import firesim.bridges._
@@ -44,12 +42,6 @@ class WithPeripheryBusFrequency(freq: BigInt) extends Config((site, here, up) =>
case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq)) case PeripheryBusKey => up(PeripheryBusKey).copy(dtsFrequency = Some(freq))
}) })
class WithPerfCounters extends Config((site, here, up) => {
case RocketTilesKey => up(RocketTilesKey) map (tile => tile.copy(
core = tile.core.copy(nPerfCounters = 29)
))
})
// Disables clock-gating; doesn't play nice with our FAME-1 pass // Disables clock-gating; doesn't play nice with our FAME-1 pass
class WithoutClockGating extends Config((site, here, up) => { class WithoutClockGating extends Config((site, here, up) => {
case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false)) case DebugModuleKey => up(DebugModuleKey, site).map(_.copy(clockGate = false))

2
generators/rocket-chip

Submodule generators/rocket-chip updated: 1872f5d501...653efa99a2

2
generators/testchipip

Submodule generators/testchipip updated: bb038feaa1...29eb87c938

183
generators/tracegen/src/main/scala/Configs.scala
View File

@@ -3,87 +3,126 @@ package tracegen
import chisel3._ import chisel3._
import chisel3.util.log2Ceil import chisel3.util.log2Ceil
import freechips.rocketchip.config.{Config, Parameters} import freechips.rocketchip.config.{Config, Parameters}
import freechips.rocketchip.groundtest.{TraceGenParams} import freechips.rocketchip.groundtest.{TraceGenParams, TraceGenTileAttachParams}
import freechips.rocketchip.subsystem.{ExtMem, SystemBusKey, WithInclusiveCache, InclusiveCacheKey} import freechips.rocketchip.subsystem._
import freechips.rocketchip.system.BaseConfig import freechips.rocketchip.system.BaseConfig
import freechips.rocketchip.rocket.DCacheParams import freechips.rocketchip.rocket.DCacheParams
import freechips.rocketchip.tile.{MaxHartIdBits, XLen} import freechips.rocketchip.tile.{MaxHartIdBits, XLen}
import scala.math.{max, min} import scala.math.{max, min}
class WithTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) class WithTraceGen(
extends Config((site, here, up) => { n: Int = 2,
case TraceGenKey => params.map { dcp => TraceGenParams( overrideIdOffset: Option[Int] = None,
dcache = Some(dcp), overrideMemOffset: Option[BigInt] = None)(
wordBits = site(XLen), params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
addrBits = 48, nReqs: Int = 8192
addrBag = { ) extends Config((site, here, up) => {
val nSets = dcp.nSets case TilesLocated(InSubsystem) => {
val nWays = dcp.nWays val prev = up(TilesLocated(InSubsystem), site)
val blockOffset = site(SystemBusKey).blockOffset val idOffset = overrideIdOffset.getOrElse(prev.size)
val nBeats = min(2, site(SystemBusKey).blockBeats) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
val beatBytes = site(SystemBusKey).beatBytes params.zipWithIndex.map { case (dcp, i) =>
List.tabulate(2 * nWays) { i => TraceGenTileAttachParams(
Seq.tabulate(nBeats) { j => tileParams = TraceGenParams(
BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) hartId = i + idOffset,
} dcache = Some(dcp),
}.flatten wordBits = site(XLen),
}, addrBits = 48,
maxRequests = nReqs, addrBag = {
memStart = site(ExtMem).get.master.base, val nSets = dcp.nSets
numGens = params.size) val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = min(2, site(SystemBusKey).blockBeats)
val beatBytes = site(SystemBusKey).beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = memOffset,
numGens = params.size),
crossingParams = RocketCrossingParams()
)
} ++ prev
} }
case MaxHartIdBits => log2Ceil(params.size + up(BoomTraceGenKey, site).length) max 1
}) })
class WithBoomTraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) class WithBoomTraceGen(
extends Config((site, here, up) => { n: Int = 2,
case BoomTraceGenKey => params.map { dcp => TraceGenParams( overrideIdOffset: Option[Int] = None,
dcache = Some(dcp), overrideMemOffset: Option[BigInt] = None)(
wordBits = site(XLen), params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nMSHRs = 4, nSets = 16, nWays = 2) },
addrBits = 48, nReqs: Int = 8192
addrBag = { ) extends Config((site, here, up) => {
val nSets = dcp.nSets case TilesLocated(InSubsystem) => {
val nWays = dcp.nWays val prev = up(TilesLocated(InSubsystem), site)
val blockOffset = site(SystemBusKey).blockOffset val idOffset = overrideIdOffset.getOrElse(prev.size)
val nBeats = min(2, site(SystemBusKey).blockBeats) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
val beatBytes = site(SystemBusKey).beatBytes params.zipWithIndex.map { case (dcp, i) =>
List.tabulate(2 * nWays) { i => BoomTraceGenTileAttachParams(
Seq.tabulate(nBeats) { j => tileParams = BoomTraceGenParams(
BigInt((j * beatBytes) + ((i * nSets) << blockOffset)) hartId = i + idOffset,
} dcache = Some(dcp),
}.flatten wordBits = site(XLen),
}, addrBits = 48,
maxRequests = nReqs, addrBag = {
memStart = site(ExtMem).get.master.base, val nSets = dcp.nSets
numGens = params.size) val nWays = dcp.nWays
val blockOffset = site(SystemBusKey).blockOffset
val nBeats = site(SystemBusKey).blockBeats
List.tabulate(nWays) { i =>
Seq.tabulate(nBeats) { j => BigInt((j * 8) + ((i * nSets) << blockOffset)) }
}.flatten
},
maxRequests = nReqs,
memStart = memOffset,
numGens = params.size),
crossingParams = RocketCrossingParams()
)
} ++ prev
} }
case MaxHartIdBits => log2Ceil(params.size + up(TraceGenKey, site).length) max 1
}) })
class WithL2TraceGen(params: Seq[DCacheParams], nReqs: Int = 8192) class WithL2TraceGen(
extends Config((site, here, up) => { n: Int = 2,
case TraceGenKey => params.map { dcp => TraceGenParams( overrideIdOffset: Option[Int] = None,
dcache = Some(dcp), overrideMemOffset: Option[BigInt] = None)(
wordBits = site(XLen), params: Seq[DCacheParams] = List.fill(n){ DCacheParams(nSets = 16, nWays = 1) },
addrBits = 48, nReqs: Int = 8192
addrBag = { ) extends Config((site, here, up) => {
val sbp = site(SystemBusKey) case TilesLocated(InSubsystem) => {
val l2p = site(InclusiveCacheKey) val prev = up(TilesLocated(InSubsystem), site)
val nSets = max(l2p.sets, dcp.nSets) val idOffset = overrideIdOffset.getOrElse(prev.size)
val nWays = max(l2p.ways, dcp.nWays) val memOffset: BigInt = overrideMemOffset.orElse(site(ExtMem).map(_.master.base)).getOrElse(0x0L)
val blockOffset = sbp.blockOffset
val nBeats = min(2, sbp.blockBeats)
val beatBytes = sbp.beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = site(ExtMem).get.master.base,
numGens = params.size)
}
case MaxHartIdBits => if (params.size == 1) 1 else log2Ceil(params.size)
})
params.zipWithIndex.map { case (dcp, i) =>
TraceGenTileAttachParams(
tileParams = TraceGenParams(
hartId = i + idOffset,
dcache = Some(dcp),
wordBits = site(XLen),
addrBits = 48,
addrBag = {
val sbp = site(SystemBusKey)
val l2p = site(InclusiveCacheKey)
val nSets = max(l2p.sets, dcp.nSets)
val nWays = max(l2p.ways, dcp.nWays)
val blockOffset = sbp.blockOffset
val nBeats = min(2, sbp.blockBeats)
val beatBytes = sbp.beatBytes
List.tabulate(2 * nWays) { i =>
Seq.tabulate(nBeats) { j =>
BigInt((j * beatBytes) + ((i * nSets) << blockOffset))
}
}.flatten
},
maxRequests = nReqs,
memStart = memOffset,
numGens = params.size),
crossingParams = RocketCrossingParams()
)
} ++ prev
}
})

53
generators/tracegen/src/main/scala/System.scala
View File

@@ -3,48 +3,29 @@ package tracegen
import chisel3._ import chisel3._
import freechips.rocketchip.config.{Field, Parameters} import freechips.rocketchip.config.{Field, Parameters}
import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams} import freechips.rocketchip.diplomacy.{LazyModule, LazyModuleImp, BufferParams}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams} import freechips.rocketchip.interrupts.{IntSinkNode, IntSinkPortSimple}
import freechips.rocketchip.groundtest.{DebugCombiner, TraceGenParams, GroundTestTile}
import freechips.rocketchip.subsystem._ import freechips.rocketchip.subsystem._
case object BoomTraceGenKey extends Field[Seq[TraceGenParams]](Nil)
case object TraceGenKey extends Field[Seq[TraceGenParams]](Nil)
trait HasTraceGenTiles { this: BaseSubsystem =>
val rocket_tiles = p(TraceGenKey).zipWithIndex.map { case (params, i) =>
LazyModule(new TraceGenTile(i, params, p))
}
val boom_tiles = p(BoomTraceGenKey).zipWithIndex.map { case (params, i) =>
LazyModule(new BoomTraceGenTile(i, params, p))
}
val tiles = rocket_tiles ++ boom_tiles
tiles.foreach { t =>
sbus.fromTile(None, buffer = BufferParams.default) { t.masterNode }
}
}
trait HasTraceGenTilesModuleImp extends LazyModuleImp {
val outer: HasTraceGenTiles
val success = IO(Output(Bool()))
outer.tiles.zipWithIndex.map { case(t, i) =>
t.module.constants.hartid := i.U
}
val status = DebugCombiner(
outer.rocket_tiles.map(_.module.status) ++
outer.boom_tiles.map(_.module.status)
)
success := status.finished
}
class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem class TraceGenSystem(implicit p: Parameters) extends BaseSubsystem
with HasTraceGenTiles with HasTiles
with CanHaveMasterAXI4MemPort { with CanHaveMasterAXI4MemPort {
def coreMonitorBundles = Nil
override lazy val module = new TraceGenSystemModuleImp(this) override lazy val module = new TraceGenSystemModuleImp(this)
} }
class TraceGenSystemModuleImp(outer: TraceGenSystem) class TraceGenSystemModuleImp(outer: TraceGenSystem)
extends BaseSubsystemModuleImp(outer) extends BaseSubsystemModuleImp(outer)
with HasTraceGenTilesModuleImp {
val success = IO(Output(Bool()))
outer.tiles.zipWithIndex.map { case(t, i) => t.module.constants.hartid := i.U }
val status = dontTouch(DebugCombiner(outer.tiles.collect {
case t: GroundTestTile => t.module.status
case t: BoomTraceGenTile => t.module.status
}))
success := outer.tileCeaseSinkNode.in.head._1.asUInt.andR
}

120
generators/tracegen/src/main/scala/Tile.scala
View File

@@ -3,36 +3,17 @@ package tracegen
import chisel3._ import chisel3._
import chisel3.util._ import chisel3.util._
import freechips.rocketchip.config.Parameters import freechips.rocketchip.config.Parameters
import freechips.rocketchip.diplomacy.{LazyModule, SynchronousCrossing} import freechips.rocketchip.diplomacy.{SimpleDevice, LazyModule, SynchronousCrossing, ClockCrossingType}
import freechips.rocketchip.groundtest.{TraceGenerator, TraceGenParams, DummyPTW, GroundTestStatus} import freechips.rocketchip.groundtest._
import freechips.rocketchip.rocket.{DCache, NonBlockingDCache, SimpleHellaCacheIF, HellaCacheExceptions, HellaCacheReq, HellaCacheIO} import freechips.rocketchip.rocket._
import freechips.rocketchip.rocket.constants.{MemoryOpConstants} import freechips.rocketchip.rocket.constants.{MemoryOpConstants}
import freechips.rocketchip.tile.{BaseTile, BaseTileModuleImp, HartsWontDeduplicate, TileKey} import freechips.rocketchip.tile._
import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode} import freechips.rocketchip.tilelink.{TLInwardNode, TLIdentityNode, TLOutwardNode, TLTempNode}
import freechips.rocketchip.interrupts._ import freechips.rocketchip.interrupts._
import freechips.rocketchip.subsystem._
import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO} import boom.lsu.{BoomNonBlockingDCache, LSU, LSUCoreIO}
import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule} import boom.common.{BoomTileParams, MicroOp, BoomCoreParams, BoomModule}
class TraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters)
extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) {
val dcache = params.dcache.map { dc => LazyModule(
if (dc.nMSHRs == 0) new DCache(hartId, crossing)
else new NonBlockingDCache(hartId))
}.get
val intInwardNode: IntInwardNode = IntIdentityNode()
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val ceaseNode: IntOutwardNode = IntIdentityNode()
val haltNode: IntOutwardNode = IntIdentityNode()
val wfiNode: IntOutwardNode = IntIdentityNode()
val masterNode = visibilityNode
masterNode := dcache.node
override lazy val module = new TraceGenTileModuleImp(this)
}
class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p) class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
with MemoryOpConstants { with MemoryOpConstants {
@@ -179,22 +160,59 @@ class BoomLSUShim(implicit p: Parameters) extends BoomModule()(p)
} }
class BoomTraceGenTile(val id: Int, val params: TraceGenParams, q: Parameters) case class BoomTraceGenTileAttachParams(
extends BaseTile(params, SynchronousCrossing(), HartsWontDeduplicate(params), q) { tileParams: BoomTraceGenParams,
crossingParams: TileCrossingParamsLike
) extends CanAttachTile {
type TileType = BoomTraceGenTile
val lookup: LookupByHartIdImpl = HartsWontDeduplicate(tileParams)
}
case class BoomTraceGenParams(
wordBits: Int,
addrBits: Int,
addrBag: List[BigInt],
maxRequests: Int,
memStart: BigInt,
numGens: Int,
dcache: Option[DCacheParams] = Some(DCacheParams()),
hartId: Int = 0
) extends InstantiableTileParams[BoomTraceGenTile]
{
def instantiate(crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters): BoomTraceGenTile = {
new BoomTraceGenTile(this, crossing, lookup)
}
val core = RocketCoreParams(nPMPs = 0) //TODO remove this
val btb = None
val icache = Some(ICacheParams())
val beuAddr = None
val blockerCtrlAddr = None
val name = None
val traceParams = TraceGenParams(wordBits, addrBits, addrBag, maxRequests, memStart, numGens, dcache, hartId)
}
class BoomTraceGenTile private(
val params: BoomTraceGenParams,
crossing: ClockCrossingType,
lookup: LookupByHartIdImpl,
q: Parameters) extends BaseTile(params, crossing, lookup, q)
with SinksExternalInterrupts
with SourcesExternalNotifications
{
def this(params: BoomTraceGenParams, crossing: TileCrossingParamsLike, lookup: LookupByHartIdImpl)(implicit p: Parameters) =
this(params, crossing.crossingType, lookup, p)
val cpuDevice: SimpleDevice = new SimpleDevice("groundtest", Nil)
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val boom_params = p.alterMap(Map(TileKey -> BoomTileParams( val boom_params = p.alterMap(Map(TileKey -> BoomTileParams(
dcache=params.dcache, dcache=params.dcache,
core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false)))) core=BoomCoreParams(nPMPs=0, numLdqEntries=32, numStqEntries=32, useVM=false))))
val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params)) val dcache = LazyModule(new BoomNonBlockingDCache(hartId)(boom_params))
val intInwardNode: IntInwardNode = IntIdentityNode() val masterNode: TLOutwardNode = TLIdentityNode() := visibilityNode := dcache.node
val intOutwardNode: IntOutwardNode = IntIdentityNode()
val slaveNode: TLInwardNode = TLIdentityNode()
val ceaseNode: IntOutwardNode = IntIdentityNode()
val haltNode: IntOutwardNode = IntIdentityNode()
val wfiNode: IntOutwardNode = IntIdentityNode()
val masterNode = visibilityNode
masterNode := dcache.node
override lazy val module = new BoomTraceGenTileModuleImp(this) override lazy val module = new BoomTraceGenTileModuleImp(this)
} }
@@ -203,8 +221,9 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
extends BaseTileModuleImp(outer){ extends BaseTileModuleImp(outer){
val status = IO(new GroundTestStatus) val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None
val tracegen = Module(new TraceGenerator(outer.params)) val tracegen = Module(new TraceGenerator(outer.params.traceParams))
tracegen.io.hartid := constants.hartid tracegen.io.hartid := constants.hartid
val ptw = Module(new DummyPTW(1)) val ptw = Module(new DummyPTW(1))
@@ -219,31 +238,14 @@ class BoomTraceGenTileModuleImp(outer: BoomTraceGenTile)
lsu.io.hellacache := DontCare lsu.io.hellacache := DontCare
lsu.io.hellacache.req.valid := false.B lsu.io.hellacache.req.valid := false.B
status.finished := tracegen.io.finished outer.reportCease(Some(tracegen.io.finished))
status.timeout.valid := tracegen.io.timeout outer.reportHalt(Some(tracegen.io.timeout))
status.timeout.bits := 0.U outer.reportWFI(None)
status.error.valid := false.B
}
class TraceGenTileModuleImp(outer: TraceGenTile)
extends BaseTileModuleImp(outer) {
val status = IO(new GroundTestStatus)
val halt_and_catch_fire = None
val ptw = Module(new DummyPTW(1))
ptw.io.requestors.head <> outer.dcache.module.io.ptw
val tracegen = Module(new TraceGenerator(outer.params))
tracegen.io.hartid := constants.hartid
val dcacheIF = Module(new SimpleHellaCacheIF())
dcacheIF.io.requestor <> tracegen.io.mem
outer.dcache.module.io.cpu <> dcacheIF.io.cache
status.finished := tracegen.io.finished
status.timeout.valid := tracegen.io.timeout status.timeout.valid := tracegen.io.timeout
status.timeout.bits := 0.U status.timeout.bits := 0.U
status.error.valid := false.B status.error.valid := false.B
assert(!tracegen.io.timeout, s"TraceGen tile ${outer.id}: request timed out") assert(!tracegen.io.timeout, s"TraceGen tile ${outer.tileParams.hartId}: request timed out")
} }

1
project/plugins.sbt
View File

@@ -15,5 +15,6 @@ addSbtPlugin("com.simplytyped" % "sbt-antlr4" % "0.8.1")
addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3") addSbtPlugin("com.github.gseitz" % "sbt-protobuf" % "0.6.3")
addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4") addSbtPlugin("ch.epfl.scala" % "sbt-scalafix" % "0.9.4")
addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1") addSbtPlugin("com.typesafe" % "sbt-mima-plugin" % "0.6.1")
addSbtPlugin("ch.epfl.scala" % "sbt-bloop" % "1.4.1")
libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1" libraryDependencies += "com.github.os72" % "protoc-jar" % "3.5.1.1"

1
scripts/firesim-setup.sh
View File

@@ -12,7 +12,6 @@ cd "${scripts_dir}/.."
# Reenable the FireSim submodule # Reenable the FireSim submodule
git config --unset submodule.sims/firesim.update || true git config --unset submodule.sims/firesim.update || true
git submodule update --init sims/firesim
cd sims/firesim cd sims/firesim
./build-setup.sh "$@" --library ./build-setup.sh "$@" --library
cd "$RDIR" cd "$RDIR"

2
sims/firesim

Submodule sims/firesim updated: c2d8e3a46e...8064d8808b

2
tools/dsptools

Submodule tools/dsptools updated: 211166e635...e32ab8a0c7

26
variables.mk
View File

@@ -125,9 +125,33 @@ JAVA_ARGS ?= -Xmx$(JAVA_HEAP_SIZE) -Xss8M -XX:MaxPermSize=256M
######################################################################################### #########################################################################################
SCALA_VERSION=2.12.10 SCALA_VERSION=2.12.10
SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION)) SCALA_VERSION_MAJOR=$(basename $(SCALA_VERSION))
SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar SBT ?= java $(JAVA_ARGS) -jar $(ROCKETCHIP_DIR)/sbt-launch.jar
BLOOP ?= bloop
BLOOP_CONFIG_DIR ?= $(base_dir)/.bloop
# This mirrors the bloop default. Set to a system-unique port in a multi-user environment
BLOOP_NAILGUN_PORT ?= 8212
SCALA_BUILDTOOL_DEPS = $(SBT_SOURCES)
ifdef ENABLE_BLOOP
override SCALA_BUILDTOOL_DEPS += $(BLOOP_CONFIG_DIR)/TIMESTAMP
# Two notes about the bloop invocation:
# 1) the sed removes a leading {file:<path>} that sometimes needs to be
# provided to SBT when a project but not for bloop.
# 2) Generally, one could could pass '--' to indicate all remaining arguments are
# destined for the scala Main, however a bug in Bloop's argument parsing causes the
# --nailgun-port argument to be lost in this case. Workaround this by prefixing
# every main-destined argument with "--args"
define run_scala_main
cd $(base_dir) && bloop --nailgun-port $(BLOOP_NAILGUN_PORT) run $(shell echo $(1) | sed 's/{.*}//') --main $(2) $(addprefix --args ,$3)
endef
else
define run_scala_main
cd $(base_dir) && $(SBT) "project $(1)" "runMain $(2) $(3)"
endef
endif
######################################################################################### #########################################################################################
# output directory for tests # output directory for tests
######################################################################################### #########################################################################################