Add a list of common config keys
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Zitao Fang
@@ -199,8 +199,8 @@ more info.
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name = portName,
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id = IdRange(0, 1 << idBits))))))
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where ``portName`` and ``idBits`` are the parameter provides by the tile. Make sure to read :::ref:`node-tyoes` to check out what
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type of nodes Chipyard supports and their parameters!
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where ``portName`` and ``idBits`` (number of bits to represent a port ID) are the parameter provides by the tile.
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Make sure to read :::ref:`node-tyoes` to check out what type of nodes Chipyard supports and their parameters!
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Also, by default, there are boundary buffers for both master and slave connections to the bus when they are leaving the tile, and you
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can override the following two functions to control how to buffer the bus requests/responses:
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@@ -291,11 +291,19 @@ The implementation class is of the following form:
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In the body of this class, you can look up any parameters by calling ``p({key})``, where ``{key}`` is the config key of
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the value you want to look up. For a list of available keys, see the appendix below.
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If you create an AXI4 node (or equivalents), you will need to connect them to your core.
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If you create an AXI4 node (or equivalents), you will need to connect them to your core. You can connect a port like this:
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.. warning::
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.. code-block:: scala
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TODO: Documenting bus connection
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outer.myAXI4Node.out foreach { case (out, edgeOut) =>
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// Connect your module IO port to "out"
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// The type of "out" here is AXI4Bundle, which is defined in generators/rocket-chip/src/main/scala/amba/axi4/Bundles.scala
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// Please refer to this file for the definition of the ports.
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// If you are using APB, check APBBundle in generators/rocket-chip/src/main/scala/amba/apb/Bundles.scala
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// If you are using AHB, check AHBSlaveBundle or AHBMasterBundle in generators/rocket-chip/src/main/scala/amba/ahb/Bundles.scala
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// (choose one depends on the type of AHB node you create)
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// If you are using AXIS, check AXISBundle and AXISBundleBits in generators/rocket-chip/src/main/scala/amba/axis/Bundles.scala
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}
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Integrate the Core
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------------------
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@@ -320,3 +328,83 @@ all custom cores. You can also create other config fragments to change other par
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Now you have finished all the steps to prepare your cores for Chipyard! To generate the custom core, simply follow the instructions
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in :::ref:`_custom_chisel` to add your project to the build system, then create a config by following the steps in :::ref:`_hetero_socs_`.
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You can now run any desired workflow for the new config just as you do for the built-in cores.
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Appendix: Common Config Keys
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----------------------------
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Chipyard provide a set of keys to store standard parameters. Below are some of the most common key used in core integration.
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(Note that internal fields are hidden)
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.. code-block:: scala
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// keys
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// Parameters exposed to the top-level design, set based on external requirements, etc. See RISC-V debug specs for more info.
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case object DebugModuleKey extends Field[Option[DebugModuleParams]](Some(DebugModuleParams()))
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case object BootROMParams extends Field[BootROMParams] // See chipyard boot process tutorial
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case object CLINTKey extends Field[Option[CLINTParams]](None) // Core Local Interrupter setting (See SiFive Interrupt Cookbook)
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case object PLICKey extends Field[Option[PLICParams]](None) // Platform Level Interrupt Controller setting (See SiFive Interrupt Cookbook)
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case object CacheBlockBytes extends Field[Int](64) // # of bytes in a cache block
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case object BroadcastKey extends Field(BroadcastParams()) // L2 Cache broadcast setting
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case object BankedL2Key extends Field(BankedL2Params()) // L2 Cache memory setting
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case object PgLevels extends Field[Int](2) // Page Level of virtual memory
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case object ASIdBits extends Field[Int](0) // Max # of bits for Address Space Identifer (See specs)
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case object ExtMem extends Field[Option[MemoryPortParams]](None) // External DRAM setting
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case object ExtBus extends Field[Option[MasterPortParams]](None) // External (off-chip) output bus setting
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case object ExtIn extends Field[Option[SlavePortParams]](None) // External (off-chip) input bus setting
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case object MaxHartIdBits extends Field[Int] // Max # of bits used to represent a Hart ID
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case object XLen extends Field[Int] // Instruction bits (32 or 64)
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case object BuildRoCC extends Field[Seq[Parameters => LazyRoCC]](Nil) // See custom ROCC tutorial
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// Values
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case class DebugModuleParams (
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nDMIAddrSize : Int = 7, // Size of the Debug Bus Address
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nProgramBufferWords: Int = 16, // Number of 32-bit words for Program Buffer
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nAbstractDataWords : Int = 4, // Number of 32-bit words for Abstract Commands
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nScratch : Int = 1, // Number of scratch memories used
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hasBusMaster : Boolean = false, // Whether or not a bus master should be included
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clockGate : Boolean = true, // Use clock gating
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maxSupportedSBAccess : Int = 32, // Maximum transaction size supported by System Bus Access logic.
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supportQuickAccess : Boolean = false, // Whether or not to support the quick access command.
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supportHartArray : Boolean = true, // Whether or not to implement the hart array register (if >1 hart).
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nHaltGroups : Int = 1, // Number of halt groups (group of harts that are halted together)
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nExtTriggers : Int = 0, // Number of extra triggers
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hasHartResets : Boolean = false, // Whether harts can be reseted with debugging system
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hasImplicitEbreak : Boolean = false, // There is an additional RO program buffer word containing an ebreak
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hasAuthentication : Boolean = false, // Has authentication (to prevent unauthorized users to use debugging system)
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crossingHasSafeReset : Boolean = true // Include "safe" logic in Async Crossings so that only one side needs to be reset.
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)
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case class CLINTParams(
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baseAddress: BigInt = 0x02000000, // Default interrupt handler base address for CLINT
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intStages: Int = 0 // # of cycles (stages) interrupts are delayed
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)
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case class PLICParams(
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baseAddress: BigInt = 0xC000000, // Default interrupt handler base address for PLIC
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maxPriorities: Int = 7, // Maximum allowed interrupt priority (cannot be over 7)
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intStages: Int = 0, // # of cycles (stages) interrupts are delayed
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maxHarts: Int = PLICConsts.maxMaxHarts // Maximum number or hart / core connected to it
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)
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case class BroadcastParams(
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nTrackers: Int = 4, // # of broadcast tracker
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bufferless: Boolean = false // Bufferless broadcast
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)
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case class BankedL2Params(
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nBanks: Int = 1 // Number of banks in L2 cache
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)
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case class MasterPortParams(
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base: BigInt, // Base memory address for this port
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size: BigInt, // Size of this external memory
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beatBytes: Int, // Interface width in bytes
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idBits: Int, // # of bits in the port ID
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maxXferBytes: Int = 256, // Maximum bytes in one transfer transaction
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executable: Boolean = true // If the data from this port can be executed as instruciton
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)
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/** Specifies the width of external slave ports */
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case class SlavePortParams(
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beatBytes: Int, // Interface width in bytes
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idBits: Int, // # of bits in the port ID
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sourceBits: Int // # of bits in the source address
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)
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case class MemoryPortParams(
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master: MasterPortParams, // The memory port setting
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nMemoryChannels: Int // Number of memory channel
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)
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