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fixing macro paths for yosys with circt generated verilog [skip ci]

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This commit is contained in:
Nayiri
2023-12-14 18:02:32 -08:00
parent 088e9ea45a
commit 42622919cd
3 changed files with 12 additions and 14 deletions
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19
vlsi/example-designs/sky130-openroad-rockettile.yml
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@@ -22,25 +22,16 @@ vlsi.inputs.placement_constraints:
bottom: 10 bottom: 10
# Place SRAM memory instances # Place SRAM memory instances
- path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0" # data cache
- path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
type: hardmacro type: hardmacro
x: 50 x: 50
y: 50 y: 50
orientation: r90 orientation: r90
- path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0" - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro type: hardmacro
x: 50 x: 50
y: 450 y: 800
orientation: r90
- path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 850
orientation: r90
- path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
type: hardmacro
x: 50
y: 1250
orientation: r90 orientation: r90
# tag array # tag array
@@ -51,7 +42,7 @@ vlsi.inputs.placement_constraints:
orientation: r90 orientation: r90
# instruction cache # instruction cache
- path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0" - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
type: hardmacro type: hardmacro
x: 50 x: 50
y: 2100 y: 2100

5
vlsi/example-sky130.yml
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@@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints:
x: 50 x: 50
y: 50 y: 50
orientation: r90 orientation: r90
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
type: hardmacro
x: 50
y: 800
orientation: r90
# tag array # tag array
- path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0" - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"

2
vlsi/tutorial.mk
View File

@@ -39,4 +39,6 @@ ifeq ($(tutorial),sky130-openroad)
example-designs/sky130-openroad-rockettile.yml, ) example-designs/sky130-openroad-rockettile.yml, )
VLSI_OBJ_DIR ?= build-sky130-openroad VLSI_OBJ_DIR ?= build-sky130-openroad
INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS) INPUT_CONFS ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
# Yosys compatibility for CIRCT-generated Verilog
ENABLE_YOSYS_FLOW = 1
endif endif