From 42622919cd4833a20db2d36d1646a313a34fe966 Mon Sep 17 00:00:00 2001
From: Nayiri <nayiri@berkeley.edu>
Date: Thu, 14 Dec 2023 18:02:32 -0800
Subject: [PATCH] fixing macro paths for yosys with circt generated verilog
 [skip ci]

---
 .../sky130-openroad-rockettile.yml            | 19 +++++--------------
 vlsi/example-sky130.yml                       |  5 +++++
 vlsi/tutorial.mk                              |  2 ++
 3 files changed, 12 insertions(+), 14 deletions(-)

diff --git a/vlsi/example-designs/sky130-openroad-rockettile.yml b/vlsi/example-designs/sky130-openroad-rockettile.yml
index 7db35c9b..4a6b664c 100644
--- a/vlsi/example-designs/sky130-openroad-rockettile.yml
+++ b/vlsi/example-designs/sky130-openroad-rockettile.yml
@@ -22,25 +22,16 @@ vlsi.inputs.placement_constraints:
       bottom: 10
 
   # Place SRAM memory instances
-  - path: "RocketTile/dcache/data/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
+    # data cache
+  - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_0_0"
     type: hardmacro
     x: 50
     y: 50
     orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_1/data_arrays_0_0_ext/mem_0_0"
+  - path: "RocketTile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
     type: hardmacro
     x: 50
-    y: 450
-    orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_2/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 850
-    orientation: r90
-  - path: "RocketTile/dcache/data/data_arrays_0_3/data_arrays_0_0_ext/mem_0_0"
-    type: hardmacro
-    x: 50
-    y: 1250
+    y: 800
     orientation: r90
 
   # tag array
@@ -51,7 +42,7 @@ vlsi.inputs.placement_constraints:
     orientation: r90
 
   # instruction cache
-  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_0_ext/mem_0_0"
+  - path: "RocketTile/frontend/icache/data_arrays_0_0/data_arrays_0_0_ext/mem_0_0"
     type: hardmacro
     x: 50
     y: 2100
diff --git a/vlsi/example-sky130.yml b/vlsi/example-sky130.yml
index 1cd281f7..1e3faf1c 100644
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints:
     x: 50
     y: 50
     orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+    type: hardmacro
+    x: 50
+    y: 800
+    orientation: r90
 
   # tag array
   - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"
diff --git a/vlsi/tutorial.mk b/vlsi/tutorial.mk
index ddafd80f..5e57455f 100644
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -39,4 +39,6 @@ ifeq ($(tutorial),sky130-openroad)
                             example-designs/sky130-openroad-rockettile.yml, )
     VLSI_OBJ_DIR      ?= build-sky130-openroad
     INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
+    # Yosys compatibility for CIRCT-generated Verilog
+    ENABLE_YOSYS_FLOW  = 1
 endif