fixing macro paths for yosys with circt generated verilog [skip ci]

2023-12-14 18:02:32 -08:00
parent 088e9ea45a
commit 42622919cd
3 changed files with 12 additions and 14 deletions
--- a/vlsi/tutorial.mk
+++ b/vlsi/tutorial.mk
@@ -39,4 +39,6 @@ ifeq ($(tutorial),sky130-openroad)
                            example-designs/sky130-openroad-rockettile.yml, )
    VLSI_OBJ_DIR      ?= build-sky130-openroad
    INPUT_CONFS       ?= $(TOOLS_CONF) $(TECH_CONF) $(DESIGN_CONFS) $(EXTRA_CONFS)
+    # Yosys compatibility for CIRCT-generated Verilog
+    ENABLE_YOSYS_FLOW  = 1
 endif