fixing macro paths for yosys with circt generated verilog [skip ci]

2023-12-14 18:02:32 -08:00
parent 088e9ea45a
commit 42622919cd
3 changed files with 12 additions and 14 deletions
--- a/vlsi/example-sky130.yml
+++ b/vlsi/example-sky130.yml
@@ -48,6 +48,11 @@ vlsi.inputs.placement_constraints:
    x: 50
    y: 50
    orientation: r90
+  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/dcache/data/data_arrays_0/data_arrays_0_ext/mem_1_0"
+    type: hardmacro
+    x: 50
+    y: 800
+    orientation: r90

  # tag array
  - path: "ChipTop/system/tile_prci_domain/tile_reset_domain_tile/frontend/icache/tag_array_0/tag_array_0_ext/mem_0_0"