ADD: organize abstract config into sections
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-T.K.-
@@ -11,6 +11,9 @@ import org.chipsalliance.cde.config.{Config}
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// --------------
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class AbstractConfig extends Config(
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// ==================================
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// Set up TestHarness
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// ==================================
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// The HarnessBinders control generation of hardware in the TestHarness
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new chipyard.harness.WithUARTAdapter ++ // add UART adapter to display UART on stdout, if uart is present
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new chipyard.harness.WithBlackBoxSimMem ++ // add SimDRAM DRAM model for axi4 backing memory, if axi4 mem is enabled
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@@ -28,6 +31,9 @@ class AbstractConfig extends Config(
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new chipyard.harness.WithResetFromHarness ++ // reset controlled by harness
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new chipyard.harness.WithAbsoluteFreqHarnessClockInstantiator ++ // generate clocks in harness with unsynthesizable ClockSourceAtFreqMHz
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// ==================================
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// Set up I/O harness
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// ==================================
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// The IOBinders instantiate ChipTop IOs to match desired digital IOs
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// IOCells are generated for "Chip-like" IOs
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new chipyard.iobinders.WithSerialTLIOCells ++
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@@ -51,38 +57,68 @@ class AbstractConfig extends Config(
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new chipyard.iobinders.WithUARTTSIPunchthrough ++
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new chipyard.iobinders.WithNMITiedOff ++
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// By default, punch out IOs to the Harness
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new chipyard.clocking.WithPassthroughClockGenerator ++
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
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new chipyard.config.WithPeripheryBusFrequency(500.0) ++ // Default 500 MHz pbus
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new chipyard.config.WithMemoryBusFrequency(500.0) ++ // Default 500 MHz mbus
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new chipyard.config.WithControlBusFrequency(500.0) ++ // Default 500 MHz cbus
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new chipyard.config.WithSystemBusFrequency(500.0) ++ // Default 500 MHz sbus
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new chipyard.config.WithFrontBusFrequency(500.0) ++ // Default 500 MHz fbus
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new chipyard.config.WithOffchipBusFrequency(500.0) ++ // Default 500 MHz obus
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new testchipip.boot.WithCustomBootPin ++ // add a custom-boot-pin to support pin-driven boot address
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new testchipip.boot.WithBootAddrReg ++ // add a boot-addr-reg for configurable boot address
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new testchipip.serdes.WithSerialTL(Seq( // add a serial-tilelink interface
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// ==================================
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// Set up Memory Devices
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// ==================================
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// External memory section
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new testchipip.serdes.WithSerialTL(Seq( /** add a serial-tilelink interface */
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testchipip.serdes.SerialTLParams(
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client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), // serial-tilelink interface will master the FBUS, and support 4 idBits
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width = 32 // serial-tilelink interface with 32 lanes
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client = Some(testchipip.serdes.SerialTLClientParams(idBits=4)), /** serial-tilelink interface will master the FBUS, and support 4 idBits */
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width = 32 /** serial-tilelink interface with 32 lanes */
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)
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)) ++
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new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ // increase debug module data capacity
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new chipyard.config.WithBootROM ++ // use default bootrom
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new chipyard.config.WithUART ++ // add a UART
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new chipyard.config.WithL2TLBs(1024) ++ // use L2 TLBs
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new chipyard.config.WithNoSubsystemDrivenClocks ++ // drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks
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new chipyard.config.WithInheritBusFrequencyAssignments ++ // Unspecified clocks within a bus will receive the bus frequency if set
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // Default 1 memory channels
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new freechips.rocketchip.subsystem.WithClockGateModel ++ // add default EICG_wrapper clock gate model
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new freechips.rocketchip.subsystem.WithJtagDTM ++ // set the debug module to expose a JTAG port
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip)
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ // use Sifive L2 cache
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts
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new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ // leave the bus clocks undriven by sbus
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2
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new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ // custom device name for DTS
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new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system
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// Peripheral section
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new chipyard.config.WithUART ++ /** add a UART */
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// Core section
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new chipyard.config.WithBootROM ++ /** use default bootrom */
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new testchipip.boot.WithCustomBootPin ++ /** add a custom-boot-pin to support pin-driven boot address */
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new testchipip.boot.WithBootAddrReg ++ /** add a boot-addr-reg for configurable boot address */
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// ==================================
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// Set up tiles
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// ==================================
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// Debug settings
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new chipyard.config.WithDebugModuleAbstractDataWords(8) ++ /** increase debug module data capacity */
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// TODO: add these fragments
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// new chipyard.config.WithJTAGDTMKey(idcodeVersion = 2, partNum = 0x000, manufId = 0x489, debugIdleCycles = 5) ++
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// new freechips.rocketchip.subsystem.WithNBreakpoints(2) ++
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new freechips.rocketchip.subsystem.WithJtagDTM ++ /** set the debug module to expose a JTAG port */
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// Cache settings
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new chipyard.config.WithL2TLBs(1024) ++ /** use L2 TLBs */
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new freechips.rocketchip.subsystem.WithInclusiveCache ++ /** use Sifive L2 cache */
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// Memory settings
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new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ /** Default 1 memory channels */
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new freechips.rocketchip.subsystem.WithNoMMIOPort ++ /** no top-level MMIO master port (overrides default set in rocketchip) */
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new freechips.rocketchip.subsystem.WithNoSlavePort ++ /** no top-level MMIO slave port (overrides default set in rocketchip) */
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new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ /** hierarchical buses including sbus/mbus/pbus/fbus/cbus/l2 */
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// Core Settings
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new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ /** no external interrupts */
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// ==================================
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// Set up reset and clocking
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// ==================================
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new freechips.rocketchip.subsystem.WithDontDriveBusClocksFromSBus ++ /** leave the bus clocks undriven by sbus */
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new freechips.rocketchip.subsystem.WithClockGateModel ++ /** add default EICG_wrapper clock gate model */
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new chipyard.clocking.WithClockGroupsCombinedByName(("uncore", Seq("sbus", "mbus", "pbus", "fbus", "cbus", "obus", "implicit"), Seq("tile"))) ++
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new chipyard.config.WithPeripheryBusFrequency(500.0) ++ /** Default 500 MHz pbus */
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new chipyard.config.WithMemoryBusFrequency(500.0) ++ /** Default 500 MHz mbus */
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new chipyard.config.WithControlBusFrequency(500.0) ++ /** Default 500 MHz cbus */
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new chipyard.config.WithSystemBusFrequency(500.0) ++ /** Default 500 MHz sbus */
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new chipyard.config.WithFrontBusFrequency(500.0) ++ /** Default 500 MHz fbus */
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new chipyard.config.WithOffchipBusFrequency(500.0) ++ /** Default 500 MHz obus */
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new chipyard.config.WithInheritBusFrequencyAssignments ++ /** Unspecified clocks within a bus will receive the bus frequency if set */
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new chipyard.config.WithNoSubsystemDrivenClocks ++ /** drive the subsystem diplomatic clocks from ChipTop instead of using implicit clocks */
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new chipyard.clocking.WithPassthroughClockGenerator ++
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// ==================================
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// Base Settings
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// ==================================
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new freechips.rocketchip.subsystem.WithDTS("ucb-bar,chipyard", Nil) ++ /** custom device name for DTS */
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new freechips.rocketchip.system.BaseConfig) /** "base" rocketchip system */
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