From 4038217ae9078362712e3370063c16d5214f25de Mon Sep 17 00:00:00 2001 From: Jerry Zhao Date: Mon, 17 Apr 2023 17:56:44 -0700 Subject: [PATCH] Serial-TL backing memory configs should use 1 memory channel --- generators/chipyard/src/main/scala/config/ChipConfigs.scala | 1 + generators/chipyard/src/main/scala/config/RocketConfigs.scala | 1 + 2 files changed, 2 insertions(+) diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index 7f875584..d98cf490 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -24,6 +24,7 @@ class ChipLikeQuadRocketConfig extends Config( new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel //================================== // Set up clock./reset diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index 8ed4acdc..965a81fc 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -125,6 +125,7 @@ class MulticlockAXIOverSerialConfig extends Config( new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new freechips.rocketchip.subsystem.WithNBigCores(2) ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel new chipyard.config.AbstractConfig) // DOC include end: MulticlockAXIOverSerialConfig