Add Rocket and Boom to CoreManager

generators/chipyard/src/main/scala/ConfigFragments.scala

@@ -148,7 +148,9 @@ class WithControlCore extends Config((site, here, up) => {
 })
 
 class WithTraceIO extends Config((site, here, up) =>
-  GenericConfig(Map("trace" -> true)) (site, here, up) orElse {
-    case BoomTilesKey => up(BoomTilesKey) map (tile => tile.copy(trace = true))
+  GenericConfig(Map("trace" -> true), {
+    case RocketTilesKey => false
+    case _ => true
+  }) (site, here, up) orElse {
     case TracePortKey => Some(TracePortParams())
   })

generators/chipyard/src/main/scala/CoreManager.scala

@@ -6,12 +6,13 @@ import scala.reflect.runtime.universe._
 import chisel3._
 
 import freechips.rocketchip.config.{Parameters, Config, Field, View}
-import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams}
+import freechips.rocketchip.subsystem.{SystemBusKey, RocketTilesKey, RocketCrossingParams, RocketCrossingKey}
 import freechips.rocketchip.diplomacy.{LazyModule, ClockCrossingType, ValName}
 import freechips.rocketchip.diplomaticobjectmodel.logicaltree.LogicalTreeNode
 import freechips.rocketchip.rocket._
 import freechips.rocketchip.tile._
 
+import boom.common.{BoomTile, BoomTilesKey, BoomCrossingKey, BoomTileParams}
 import ariane.{ArianeTile, ArianeTilesKey, ArianeCrossingKey, ArianeTileParams}
 import chipsalliance.rocketchip.config.Parameters
 
@@ -34,7 +35,7 @@ class CoreEntry[TileParamsT <: TileParams with Product: TypeTag, TileT <: BaseTi
   private val paramCtr = paramClass.getConstructors.head
 
   private val tileClass = mirror.runtimeClass(typeOf[TileT].typeSymbol.asClass)
-  private val tileCtr = tileClass.getConstructors.head
+  private val tileCtr = tileClass.getConstructors.filter(ctr => ctr.getParameterTypes()(4) == classOf[Parameters]).head
 
   // Reflective version of copy()
   def copyTileParam(tileParam: TileParamsT, properties: Map[String, Any]) = {
@@ -82,6 +83,8 @@ object GenericConfig {
 object CoreManager {
   val cores: List[CoreEntryBase] = List(
     // ADD YOUR CORE DEFINITION HERE
+    new CoreEntry[RocketTileParams, RocketTile](RocketTilesKey, RocketCrossingKey),
+    new CoreEntry[BoomTileParams, BoomTile](BoomTilesKey, BoomCrossingKey),
     new CoreEntry[ArianeTileParams, ArianeTile](ArianeTilesKey, ArianeCrossingKey)
   )
 }

generators/chipyard/src/main/scala/Subsystem.scala

@@ -33,29 +33,7 @@ trait HasChipyardTiles extends HasTiles
 
   val module: HasChipyardTilesModuleImp
 
-  protected val rocketTileParams = p(RocketTilesKey)
-  protected val boomTileParams = p(BoomTilesKey)
-
-  // crossing can either be per tile or global (aka only 1 crossing specified)
-  private val rocketCrossings = perTileOrGlobalSetting(p(RocketCrossingKey), rocketTileParams.size)
-  private val boomCrossings = perTileOrGlobalSetting(p(BoomCrossingKey), boomTileParams.size)
-
-  private val rocketTilesInfo = (rocketTileParams zip rocketCrossings) map {
-    case (param, crossing) => (
-      param,
-      crossing,
-      LazyModule(new RocketTile(param, crossing, PriorityMuxHartIdFromSeq(rocketTileParams), logicalTreeNode))
-    )
-  }
-  private val boomTilesInfo = (boomTileParams zip boomCrossings) map {
-    case (param, crossing) => (
-      param,
-      crossing,
-      LazyModule(new BoomTile(param, crossing, PriorityMuxHartIdFromSeq(boomTileParams), logicalTreeNode))
-    )
-  }
-
-  val allTilesInfo = rocketTilesInfo ++ boomTilesInfo ++
+  val allTilesInfo: Seq[(TileParams, RocketCrossingParams, BaseTile)] = 
     (CoreManager.cores flatMap (core => core.instantiateTile(perTileOrGlobalSetting _, logicalTreeNode)))
 
   // Make a tile and wire its nodes into the system,

generators/chipyard/src/main/scala/TestSuites.scala

@@ -62,86 +62,6 @@ class TestSuiteHelper
   def addSuite(s: RocketTestSuite) { suites += (s.makeTargetName -> s) }
   def addSuites(s: Seq[RocketTestSuite]) { s.foreach(addSuite) }
 
-  /**
-  * Add BOOM tests (asm, bmark, regression)
-  */
-  def addBoomTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(BoomTilesKey).find(_.hartId == 0).map { tileParams =>
-      val coreParams = tileParams.core
-      val vm = coreParams.useVM
-      val env = if (vm) List("p","v") else List("p")
-      coreParams.fpu foreach { case cfg =>
-        if (xlen == 32) {
-          addSuites(env.map(rv32uf))
-          if (cfg.fLen >= 64) {
-            addSuites(env.map(rv32ud))
-          }
-        } else if (cfg.fLen >= 64) {
-          addSuites(env.map(rv64ud))
-          addSuites(env.map(rv64uf))
-          addSuite(rv32udBenchmarks)
-        }
-      }
-      if (coreParams.useAtomics) {
-        if (tileParams.dcache.flatMap(_.scratch).isEmpty) {
-          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-        } else {
-          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-        }
-      }
-      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-      val (rvi, rvu) =
-        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-        else            ((if (vm) rv32i else rv32pi), rv32u)
-
-      addSuites(rvi.map(_("p")))
-      addSuites(rvu.map(_("p")))
-      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-      addSuite(benchmarks)
-      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-    }
-  }
-
-  /**
-  * Add Rocket tests (asm, bmark, regression)
-  */
-  def addRocketTestSuites(implicit p: Parameters) = {
-    val xlen = p(XLen)
-    p(RocketTilesKey).find(_.hartId == 0).map { tileParams =>
-      val coreParams = tileParams.core
-      val vm = coreParams.useVM
-      val env = if (vm) List("p","v") else List("p")
-      coreParams.fpu foreach { case cfg =>
-        if (xlen == 32) {
-          addSuites(env.map(rv32uf))
-          if (cfg.fLen >= 64)
-            addSuites(env.map(rv32ud))
-        } else {
-          addSuite(rv32udBenchmarks)
-          addSuites(env.map(rv64uf))
-          if (cfg.fLen >= 64)
-            addSuites(env.map(rv64ud))
-        }
-      }
-      if (coreParams.useAtomics) {
-        if (tileParams.dcache.flatMap(_.scratch).isEmpty)
-          addSuites(env.map(if (xlen == 64) rv64ua else rv32ua))
-        else
-          addSuites(env.map(if (xlen == 64) rv64uaSansLRSC else rv32uaSansLRSC))
-      }
-      if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
-      val (rvi, rvu) =
-        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
-        else            ((if (vm) rv32i else rv32pi), rv32u)
-
-      addSuites(rvi.map(_("p")))
-      addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
-      addSuite(benchmarks)
-      addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))
-    }
-  }
-
   /**
   * Add third-party core (including Ariane) tests (asm, bmark, regression)
   */
@@ -175,6 +95,7 @@ class TestSuiteHelper
         else            ((if (vm) rv32i else rv32pi), rv32u)
 
       addSuites(rvi.map(_("p")))
+      addSuites(rvu.map(_("p")))
       addSuites((if (vm) List("v") else List()).flatMap(env => rvu.map(_(env))))
       addSuite(benchmarks)
       addSuite(new RegressionTestSuite(if (xlen == 64) rv64RegrTestNames else rv32RegrTestNames))

generators/chipyard/src/main/scala/stage/phases/AddDefaultTests.scala

@@ -33,11 +33,8 @@ class AddDefaultTests extends Phase with PreservesAll[Phase] with HasRocketChipS
     val suiteHelper = new TestSuiteHelper
     // Use Xlen as a proxy for detecting if we are a processor-like target
     // The underlying test suites expect this field to be defined
-    if (p.lift(XLen).nonEmpty) {
-      suiteHelper.addRocketTestSuites
-      suiteHelper.addBoomTestSuites
+    if (p.lift(XLen).nonEmpty)
       CoreManager.cores map (core => suiteHelper.addThirdPartyTestSuites(core.tileParamsLookup))
-    }
 
     // if hwacha parameter exists then generate its tests
     // TODO: find a more elegant way to do this. either through