add PWM example

src/main/scala/Configs.scala

@@ -11,8 +11,17 @@ class WithExampleTop extends Config(
     case _ => throw new CDEMatchError
   })
 
+class WithPWM extends Config(
+  (pname, site, here) => pname match {
+    case BuildExampleTop => (p: Parameters) => LazyModule(new ExampleTopWithPWM(p))
+    case _ => throw new CDEMatchError
+  })
+
 class SerialAdapterConfig extends Config(
   new WithSerialAdapter ++ new rocketchip.BaseConfig)
 
 class DefaultExampleConfig extends Config(
   new WithExampleTop ++ new SerialAdapterConfig)
+
+class PWMExampleConfig extends Config(
+  new WithPWM ++ new SerialAdapterConfig)

src/main/scala/PWM.scala

@@ -0,0 +1,75 @@
+package example
+
+import chisel3._
+import chisel3.util._
+import cde.Parameters
+import uncore.tilelink._
+import junctions._
+import diplomacy._
+import rocketchip._
+
+class PWM(implicit p: Parameters) extends Module {
+  val io = new Bundle {
+    val pwmout = Bool(OUTPUT)
+    val tl = (new ClientUncachedTileLinkIO).flip
+  }
+
+  val period = Reg(UInt(width = 64))
+  val duty = Reg(UInt(width = 64))
+  val enable = Reg(init = Bool(false))
+  val counter = Reg(UInt(width = 64))
+
+  when (counter >= period) {
+    counter := UInt(0)
+  } .otherwise {
+    counter := counter + UInt(1)
+  }
+
+  io.pwmout := enable && (counter < duty)
+
+  val acq = Queue(io.tl.acquire, 1)
+  val addr = Cat(acq.bits.addr_block, acq.bits.addr_beat)
+
+  io.tl.grant.valid := acq.valid
+  acq.ready := io.tl.grant.ready
+  io.tl.grant.bits := Grant(
+    is_builtin_type = Bool(true),
+    g_type = acq.bits.getBuiltInGrantType(),
+    client_xact_id = acq.bits.client_xact_id,
+    manager_xact_id = UInt(0),
+    addr_beat = acq.bits.addr_beat,
+    data = MuxLookup(addr, UInt(0), Seq(
+      UInt(0) -> period,
+      UInt(1) -> duty,
+      UInt(2) -> enable)))
+
+  when (acq.fire() && acq.bits.hasData()) {
+    switch (addr) {
+      is (UInt(0)) { period := acq.bits.data }
+      is (UInt(1)) { duty   := acq.bits.data }
+      is (UInt(2)) { enable := acq.bits.data(0) }
+    }
+  }
+
+  require(io.tl.tlDataBits == 64)
+}
+
+trait PeripheryPWM extends LazyModule {
+  val pDevices: ResourceManager[AddrMapEntry]
+
+  pDevices.add(AddrMapEntry("pwm", MemSize(4096, MemAttr(AddrMapProt.RW))))
+}
+
+trait PeripheryPWMBundle {
+  val pwmout = Bool(OUTPUT)
+}
+
+trait PeripheryPWMModule extends HasPeripheryParameters {
+  implicit val p: Parameters
+  val pBus: TileLinkRecursiveInterconnect
+  val io: PeripheryPWMBundle
+
+  val pwm = Module(new PWM()(outerMMIOParams))
+  pwm.io.tl <> pBus.port("pwm")
+  io.pwmout := pwm.io.pwmout
+}

src/main/scala/Top.scala

@@ -17,8 +17,20 @@ class ExampleTopBundle(p: Parameters) extends BaseTopBundle(p)
   with PeripheryBootROMBundle with PeripheryCoreplexLocalInterrupterBundle
   with PeripheryMasterMemBundle with PeripherySerialBundle
 
-class ExampleTopModule(p: Parameters, l: ExampleTop, b: => ExampleTopBundle)
+class ExampleTopModule[+L <: ExampleTop, +B <: ExampleTopBundle](p: Parameters, l: L, b: => B)
   extends BaseTopModule(p, l, b)
   with PeripheryBootROMModule with PeripheryCoreplexLocalInterrupterModule
   with PeripheryMasterMemModule with PeripherySerialModule
   with HardwiredResetVector with DirectConnection with NoDebug
+
+class ExampleTopWithPWM(q: Parameters) extends ExampleTop(q)
+    with PeripheryPWM {
+  override lazy val module = Module(
+    new ExampleTopWithPWMModule(p, this, new ExampleTopWithPWMBundle(p)))
+}
+
+class ExampleTopWithPWMBundle(p: Parameters) extends ExampleTopBundle(p)
+  with PeripheryPWMBundle
+
+class ExampleTopWithPWMModule(p: Parameters, l: ExampleTopWithPWM, b: => ExampleTopWithPWMBundle)
+  extends ExampleTopModule(p, l, b) with PeripheryPWMModule