Add CI for Arty/VCU118 (just verilog)

This commit is contained in:
abejgonzalez
2020-11-07 17:27:19 -08:00
parent 9c12ce08b7
commit 38a6bae872
5 changed files with 89 additions and 5 deletions

View File

@@ -120,6 +120,15 @@ dir="vlsi"
branches=("master")
search
submodules=("fpga-shells")
dir="fpga"
if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
then
branches=("master")
else
branches=("master" "dev")
fi
search
# turn off verbose printing to make this easier to read
set +x