From 38a6bae872fa99428e00bcc051614b16bba9bd26 Mon Sep 17 00:00:00 2001 From: abejgonzalez Date: Sat, 7 Nov 2020 17:27:19 -0800 Subject: [PATCH] Add CI for Arty/VCU118 (just verilog) --- .circleci/README.md | 18 ++++++++---- .circleci/check-commit.sh | 9 ++++++ .circleci/config.yml | 10 +++++++ .circleci/defaults.sh | 5 ++++ .circleci/do-fpga-rtl-build.sh | 52 ++++++++++++++++++++++++++++++++++ 5 files changed, 89 insertions(+), 5 deletions(-) create mode 100755 .circleci/do-fpga-rtl-build.sh diff --git a/.circleci/README.md b/.circleci/README.md index a50fc44a..0c53405d 100644 --- a/.circleci/README.md +++ b/.circleci/README.md @@ -34,11 +34,19 @@ Here the key is built from a string where the `checksum` portion converts the fi This directory contains all the collateral for the Chipyard CI to work. The following is included: - `build-toolchains.sh` # build either riscv-tools or esp-tools - `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work - `do-rtl-build.sh` # use verilator to build a sim executable (remotely) - `config.yml` # main circleci config script to enumerate jobs/workflows - `defaults.sh` # default variables used + `build-toolchains.sh` # build either riscv-tools or esp-tools + `create-hash.sh` # create hashes of riscv-tools/esp-tools so circleci caching can work + `do-rtl-build.sh` # use verilator to build a sim executable (remotely) + `config.yml` # main circleci config script to enumerate jobs/workflows + `defaults.sh` # default variables used + `check-commit.sh` # check that submodule commits are valid + `build-extra-tests.sh` # build default chipyard tests located in tests/ + `clean-old-files.sh` # clean up build server files + `do-fpga-rtl-build.sh` # similar to `do-rtl-build` but using fpga/ + `install-verilator.sh` # install verilator on build server + `run-firesim-scala-tests.sh` # run firesim scala tests + `run-tests.sh # run tests for a specific set of designs + `images/` # docker image used in CI How things are setup for Chipyard --------------------------------- diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 68cc975c..51e56449 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -120,6 +120,15 @@ dir="vlsi" branches=("master") search +submodules=("fpga-shells") +dir="fpga" +if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] +then + branches=("master") +else + branches=("master" "dev") +fi +search # turn off verbose printing to make this easier to read set +x diff --git a/.circleci/config.yml b/.circleci/config.yml index 4ee84ced..f5130930 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -361,6 +361,12 @@ jobs: project-key: "firesim-multiclock" run-script: "run-firesim-scala-tests.sh" timeout: "20m" + prepare-chipyard-fpga: + executor: main-env + steps: + - prepare-rtl: + group-key: "group-fpga" + build-script: "do-fpga-rtl-build.sh" # Order and dependencies of jobs to run workflows: @@ -500,4 +506,8 @@ workflows: - install-verilator - build-extra-tests + # Prepare the fpga builds (just Verilog) + - prepare-chipyard-fpga: + requires: + - install-riscv-toolchain diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e628de7b..0b6b6fc9 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -33,6 +33,7 @@ REMOTE_ESP_DIR=$REMOTE_WORK_DIR/esp-tools-install REMOTE_CHIPYARD_DIR=$REMOTE_WORK_DIR/chipyard REMOTE_SIM_DIR=$REMOTE_CHIPYARD_DIR/sims/verilator REMOTE_FIRESIM_DIR=$REMOTE_CHIPYARD_DIR/sims/firesim/sim +REMOTE_FPGA_DIR=$REMOTE_CHIPYARD_DIR/fpga # Disable the supershell to greatly improve the readability of SBT output when captured by Circle CI REMOTE_JAVA_ARGS="-Xmx9G -Xss8M -Dsbt.ivy.home=$REMOTE_WORK_DIR/.ivy2 -Dsbt.supershell=false -Dsbt.global.base=$REMOTE_WORK_DIR/.sbt -Dsbt.boot.directory=$REMOTE_WORK_DIR/.sbt/boot" REMOTE_VERILATOR_DIR=$REMOTE_PREFIX-$CIRCLE_SHA1-verilator-install @@ -52,6 +53,7 @@ grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spifl grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" grouping["group-other"]="icenet testchipip" +grouping["group-fpga"]="arty vcu118" # key value store to get the build strings declare -A mapping @@ -81,3 +83,6 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" + +mapping["arty"]="SUB_PROJECT=arty verilog" +mapping["vcu118"]="SUB_PROJECT=vcu118 verilog" diff --git a/.circleci/do-fpga-rtl-build.sh b/.circleci/do-fpga-rtl-build.sh new file mode 100755 index 00000000..29a5dac2 --- /dev/null +++ b/.circleci/do-fpga-rtl-build.sh @@ -0,0 +1,52 @@ +#!/bin/bash + +# create the different verilator builds +# argument is the make command string + +# turn echo on and error on earliest command +set -ex + +# get shared variables +SCRIPT_DIR="$( cd "$( dirname "$0" )" && pwd )" +source $SCRIPT_DIR/defaults.sh + +# call clean on exit +trap clean EXIT + +cd $LOCAL_CHIPYARD_DIR +./scripts/init-submodules-no-riscv-tools.sh + +# set stricthostkeychecking to no (must happen before rsync) +run "echo \"Ping $SERVER\"" + +clean + +# copy over riscv/esp-tools, and chipyard to remote +run "mkdir -p $REMOTE_CHIPYARD_DIR" +copy $LOCAL_CHIPYARD_DIR/ $SERVER:$REMOTE_CHIPYARD_DIR + +run "cp -r ~/.ivy2 $REMOTE_WORK_DIR" +run "cp -r ~/.sbt $REMOTE_WORK_DIR" + +TOOLS_DIR=$REMOTE_RISCV_DIR +LD_LIB_DIR=$REMOTE_RISCV_DIR/lib + +run "mkdir -p $REMOTE_RISCV_DIR" +copy $LOCAL_RISCV_DIR/ $SERVER:$REMOTE_RISCV_DIR + +# enter the verilator directory and build the specific config on remote server +run "export RISCV=\"$TOOLS_DIR\"; \ + make -C $REMOTE_FPGA_DIR clean;" + +read -a keys <<< ${grouping[$1]} + +for key in "${keys[@]}" +do + run "export RISCV=\"$TOOLS_DIR\"; \ + export LD_LIBRARY_PATH=\"$LD_LIB_DIR\"; \ + export PATH=\"$REMOTE_VERILATOR_DIR/bin:\$PATH\"; \ + export COURSIER_CACHE=\"$REMOTE_WORK_DIR/.coursier-cache\"; \ + make -j$REMOTE_MAKE_NPROC -C $REMOTE_FPGA_DIR FIRRTL_LOGLEVEL=info JAVA_ARGS=\"$REMOTE_JAVA_ARGS\" ${mapping[$key]}" +done + +run "rm -rf $REMOTE_CHIPYARD_DIR/project"