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Support uni-directional TLSerdesser

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This commit is contained in:
Jerry Zhao
2023-05-13 13:46:28 -07:00
parent 27f78da07b
commit 3330c23193
9 changed files with 19 additions and 48 deletions
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9
generators/firechip/src/main/scala/BridgeBinders.scala
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@@ -113,10 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
implicit val p = GetSystemParameters(system)
p(SerialTLKey).map({ sVal =>
require(sVal.axiMemOverSerialTLParams.isDefined)
val axiDomainParams = sVal.axiMemOverSerialTLParams.get
require(sVal.isMemoryDevice)
val serialManagerParams = sVal.serialManagerParams.get
val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get
require(serialManagerParams.isMemoryDevice)
val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations])
ports.map({ port =>
@@ -137,7 +136,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({
TSIBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool)
// connect SimAxiMem
(harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) =>
(harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi4, edge) =>
val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth,
axi4.bits.ar.bits.addr.getWidth,
axi4.bits.ar.bits.id.getWidth)