diff --git a/generators/chipyard/src/main/scala/config/ChipConfigs.scala b/generators/chipyard/src/main/scala/config/ChipConfigs.scala index e51ac525..9ec14314 100644 --- a/generators/chipyard/src/main/scala/config/ChipConfigs.scala +++ b/generators/chipyard/src/main/scala/config/ChipConfigs.scala @@ -21,8 +21,8 @@ class ChipLikeQuadRocketConfig extends Config( // Set up I/O //================================== new testchipip.WithSerialTLWidth(4) ++ + new testchipip.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol new chipyard.harness.WithSimAXIMemOverSerialTL ++ // Attach fast SimDRAM to TestHarness - new chipyard.config.WithSerialTLBackingMemory ++ // Backing memory is over serial TL protocol new freechips.rocketchip.subsystem.WithExtMemSize((1 << 30) * 4L) ++ // 4GB max external memory new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel diff --git a/generators/chipyard/src/main/scala/config/RocketConfigs.scala b/generators/chipyard/src/main/scala/config/RocketConfigs.scala index ea00f8b2..772eda6c 100644 --- a/generators/chipyard/src/main/scala/config/RocketConfigs.scala +++ b/generators/chipyard/src/main/scala/config/RocketConfigs.scala @@ -13,9 +13,6 @@ class RocketConfig extends Config( class TinyRocketConfig extends Config( new chipyard.iobinders.WithDontTouchIOBinders(false) ++ // TODO FIX: Don't dontTouch the ports - new chipyard.config.WithTLSerialLocation( - freechips.rocketchip.subsystem.FBUS, - freechips.rocketchip.subsystem.PBUS) ++ // attach TL serial adapter to f/p busses new freechips.rocketchip.subsystem.WithIncoherentBusTopology ++ // use incoherent bus topology new freechips.rocketchip.subsystem.WithNBanks(0) ++ // remove L2$ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove backing memory @@ -56,7 +53,6 @@ class GB1MemoryRocketConfig extends Config( // DOC include start: l1scratchpadrocket class ScratchpadOnlyRocketConfig extends Config( - new testchipip.WithSerialPBusMem ++ new chipyard.config.WithL2TLBs(0) ++ new freechips.rocketchip.subsystem.WithNBanks(0) ++ new freechips.rocketchip.subsystem.WithNoMemPort ++ // remove offchip mem port @@ -122,7 +118,7 @@ class MulticlockAXIOverSerialConfig extends Config( AsynchronousCrossing().sourceSync) ++ new chipyard.harness.WithSimAXIMemOverSerialTL ++ // add SimDRAM DRAM model for axi4 backing memory over the SerDes link, if axi4 mem is enabled - new chipyard.config.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory + new testchipip.WithSerialTLBackingMemory ++ // remove axi4 mem port in favor of SerialTL memory new freechips.rocketchip.subsystem.WithNBigCores(2) ++ new freechips.rocketchip.subsystem.WithNMemoryChannels(1) ++ // 1 memory channel diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 24eb1f4d..4181083c 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -8,7 +8,6 @@ class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -18,7 +17,6 @@ class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -28,7 +26,6 @@ class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -38,7 +35,6 @@ class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -48,7 +44,6 @@ class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -58,7 +53,6 @@ class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ new testchipip.WithSerialTLWidth(32) ++ - new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNoMemPort ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ diff --git a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala index 8caed688..4c1fc303 100644 --- a/generators/chipyard/src/main/scala/config/SpikeConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SpikeConfigs.scala @@ -27,7 +27,6 @@ class SpikeFastUARTConfig extends Config( class SpikeUltraFastConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new testchipip.WithSerialPBusMem ++ new chipyard.config.WithUARTFIFOEntries(128, 128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ @@ -48,7 +47,6 @@ class SpikeUltraFastDevicesConfig extends Config( new chipyard.WithSpikeTCM ++ new chipyard.WithNSpikeCores(1) ++ - new testchipip.WithSerialPBusMem ++ new chipyard.config.WithUARTFIFOEntries(128, 128) ++ new chipyard.config.WithMemoryBusFrequency(2) ++ new chipyard.config.WithPeripheryBusFrequency(2) ++ diff --git a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala index 56cd3bb6..3b607ae0 100644 --- a/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala +++ b/generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala @@ -59,27 +59,11 @@ class WithNoDebug extends Config((site, here, up) => { case DebugModuleKey => None }) -class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => { - case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere) -}) - class WithTLBackingMemory extends Config((site, here, up) => { case ExtMem => None // disable AXI backing memory case ExtTLMem => up(ExtMem, site) // enable TL backing memory }) -class WithSerialTLBackingMemory extends Config((site, here, up) => { - case ExtMem => None - case SerialTLKey => up(SerialTLKey, site).map { k => k.copy( - memParams = { - val memPortParams = up(ExtMem, site).get - require(memPortParams.nMemoryChannels == 1) - memPortParams.master - }, - isMemoryDevice = true - )} -}) - class WithExtMemIdBits(n: Int) extends Config((site, here, up) => { case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n))) }) diff --git a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala index 55b414cf..6a62aa46 100644 --- a/generators/chipyard/src/main/scala/example/FlatTestHarness.scala +++ b/generators/chipyard/src/main/scala/example/FlatTestHarness.scala @@ -40,9 +40,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { // Serialized TL val sVal = p(SerialTLKey).get - require(sVal.axiMemOverSerialTLParams.isDefined) - require(sVal.isMemoryDevice) - val axiDomainParams = sVal.axiMemOverSerialTLParams.get + val serialManagerParams = sVal.serialManagerParams.get + val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get + require(serialManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(lazyDut.system) withClockAndReset(clock, reset) { @@ -59,9 +59,9 @@ class FlatTestHarness(implicit val p: Parameters) extends Module { io.success := SimTSI.connect(Some(harnessMultiClockAXIRAM.module.io.tsi), clock, reset) // connect SimDRAM from the AXI port coming from the harness multi clock axi ram - (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => - val memSize = sVal.memParams.size - val memBase = sVal.memParams.base + (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => + val memSize = serialManagerParams.memParams.size + val memBase = serialManagerParams.memParams.base val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits diff --git a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala index d78318f8..7e97f5ff 100644 --- a/generators/chipyard/src/main/scala/harness/HarnessBinders.scala +++ b/generators/chipyard/src/main/scala/harness/HarnessBinders.scala @@ -145,9 +145,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ implicit val p = chipyard.iobinders.GetSystemParameters(system) p(SerialTLKey).map({ sVal => - require(sVal.axiMemOverSerialTLParams.isDefined) - val axiDomainParams = sVal.axiMemOverSerialTLParams.get - require(sVal.isMemoryDevice) + val serialManagerParams = sVal.serialManagerParams.get + val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get + require(serialManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) @@ -167,9 +167,9 @@ class WithSimAXIMemOverSerialTL extends OverrideHarnessBinder({ when (success) { th.success := true.B } // connect SimDRAM from the AXI port coming from the harness multi clock axi ram - (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi_port, edge) => - val memSize = sVal.memParams.size - val memBase = sVal.memParams.base + (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi_port, edge) => + val memSize = serialManagerParams.memParams.size + val memBase = serialManagerParams.memParams.base val lineSize = p(CacheBlockBytes) val mem = Module(new SimDRAM(memSize, lineSize, BigInt(memFreq.toLong), memBase, edge.bundle)).suggestName("simdram") mem.io.axi <> axi_port.bits diff --git a/generators/firechip/src/main/scala/BridgeBinders.scala b/generators/firechip/src/main/scala/BridgeBinders.scala index 579c2d50..0def2e38 100644 --- a/generators/firechip/src/main/scala/BridgeBinders.scala +++ b/generators/firechip/src/main/scala/BridgeBinders.scala @@ -113,10 +113,9 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ implicit val p = GetSystemParameters(system) p(SerialTLKey).map({ sVal => - require(sVal.axiMemOverSerialTLParams.isDefined) - val axiDomainParams = sVal.axiMemOverSerialTLParams.get - require(sVal.isMemoryDevice) - + val serialManagerParams = sVal.serialManagerParams.get + val axiDomainParams = serialManagerParams.axiMemOverSerialTLParams.get + require(serialManagerParams.isMemoryDevice) val memFreq = axiDomainParams.getMemFrequency(system.asInstanceOf[HasTileLinkLocations]) ports.map({ port => @@ -137,7 +136,7 @@ class WithAXIOverSerialTLCombinedBridges extends OverrideHarnessBinder({ TSIBridge(th.buildtopClock, harnessMultiClockAXIRAM.module.io.tsi, Some(MainMemoryConsts.globalName), th.buildtopReset.asBool) // connect SimAxiMem - (harnessMultiClockAXIRAM.mem_axi4 zip harnessMultiClockAXIRAM.memNode.edges.in).map { case (axi4, edge) => + (harnessMultiClockAXIRAM.mem_axi4.get zip harnessMultiClockAXIRAM.memNode.get.edges.in).map { case (axi4, edge) => val nastiKey = NastiParameters(axi4.bits.r.bits.data.getWidth, axi4.bits.ar.bits.addr.getWidth, axi4.bits.ar.bits.id.getWidth) diff --git a/generators/testchipip b/generators/testchipip index ebf61569..862a5db4 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit ebf61569c5a65ff46ac3ee77fcc3a8404441ab9d +Subproject commit 862a5db434d67eb6c4482b2e8bfa81381d9c6314