Support uni-directional TLSerdesser

generators/chipyard/src/main/scala/config/fragments/PeripheralFragments.scala

@@ -59,27 +59,11 @@ class WithNoDebug extends Config((site, here, up) => {
   case DebugModuleKey => None
 })
 
-class WithTLSerialLocation(masterWhere: TLBusWrapperLocation, slaveWhere: TLBusWrapperLocation) extends Config((site, here, up) => {
-  case SerialTLAttachKey => up(SerialTLAttachKey, site).copy(masterWhere = masterWhere, slaveWhere = slaveWhere)
-})
-
 class WithTLBackingMemory extends Config((site, here, up) => {
   case ExtMem => None // disable AXI backing memory
   case ExtTLMem => up(ExtMem, site) // enable TL backing memory
 })
 
-class WithSerialTLBackingMemory extends Config((site, here, up) => {
-  case ExtMem => None
-  case SerialTLKey => up(SerialTLKey, site).map { k => k.copy(
-    memParams = {
-      val memPortParams = up(ExtMem, site).get
-      require(memPortParams.nMemoryChannels == 1)
-      memPortParams.master
-    },
-    isMemoryDevice = true
-  )}
-})
-
 class WithExtMemIdBits(n: Int) extends Config((site, here, up) => {
   case ExtMem => up(ExtMem, site).map(x => x.copy(master = x.master.copy(idBits = n)))
 })