wu-arch/chipyard
1
0
Fork 0
Code Issues Pull Requests Actions 1 Packages Projects Releases Wiki Activity

Fix formatting

Browse Source
This commit is contained in:
joey0320
2022-12-23 20:38:40 -08:00
parent 850f613a14
commit 2dfa1847e7
2 changed files with 5 additions and 6 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/main/scala/barstools/tapeout/transforms/GenerateTopAndHarness.scala
View File

@@ -14,8 +14,8 @@ import logger.LazyLogging
// Requires two phases, one to collect modules below synTop in the hierarchy // Requires two phases, one to collect modules below synTop in the hierarchy
// and a second to remove those modules to generate the test harness // and a second to remove those modules to generate the test harness
private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging { private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s } val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h } val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
val annoFiles: List[String] = annotations.flatMap { val annoFiles: List[String] = annotations.flatMap {
case InputAnnotationFileAnnotation(f) => Some(f) case InputAnnotationFileAnnotation(f) => Some(f)
@@ -25,7 +25,7 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
// Dump firrtl and annotation files // Dump firrtl and annotation files
protected def dump( protected def dump(
circuit: Circuit, circuit: Circuit,
annotations: AnnotationSeq, annotations: AnnotationSeq
): Unit = { ): Unit = {
outAnno.foreach { annoPath => outAnno.foreach { annoPath =>
val outputFile = new java.io.PrintWriter(annoPath) val outputFile = new java.io.PrintWriter(annoPath)
@@ -34,7 +34,7 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
case _: EmittedComponent => false case _: EmittedComponent => false
case _: EmittedAnnotation[_] => false case _: EmittedAnnotation[_] => false
case _: FirrtlCircuitAnnotation => false case _: FirrtlCircuitAnnotation => false
case _: OutAnnoAnnotation => false case _: OutAnnoAnnotation => false
case _ => true case _ => true
}))) })))
outputFile.close() outputFile.close()

3
src/main/scala/barstools/tapeout/transforms/stage/TapeoutStage.scala
View File

@@ -46,7 +46,7 @@ trait TapeoutCli {
Seq( Seq(
OutAnnoAnnotation, OutAnnoAnnotation,
HarnessConfAnnotation, HarnessConfAnnotation
).foreach(_.addOptions(parser)) ).foreach(_.addOptions(parser))
} }
@@ -66,4 +66,3 @@ class TapeoutStage(doHarness: Boolean) extends Stage {
annotations annotations
} }
} }