Fix formatting
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@@ -14,8 +14,8 @@ import logger.LazyLogging
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// Requires two phases, one to collect modules below synTop in the hierarchy
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// and a second to remove those modules to generate the test harness
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private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogging {
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val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
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val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
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val outAnno: Option[String] = annotations.collectFirst { case OutAnnoAnnotation(s) => s }
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val harnessConf: Option[String] = annotations.collectFirst { case HarnessConfAnnotation(h) => h }
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val annoFiles: List[String] = annotations.flatMap {
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case InputAnnotationFileAnnotation(f) => Some(f)
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@@ -25,7 +25,7 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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// Dump firrtl and annotation files
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protected def dump(
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circuit: Circuit,
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annotations: AnnotationSeq,
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annotations: AnnotationSeq
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): Unit = {
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outAnno.foreach { annoPath =>
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val outputFile = new java.io.PrintWriter(annoPath)
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@@ -34,7 +34,7 @@ private class GenerateTopAndHarness(annotations: AnnotationSeq) extends LazyLogg
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case _: EmittedComponent => false
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case _: EmittedAnnotation[_] => false
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case _: FirrtlCircuitAnnotation => false
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case _: OutAnnoAnnotation => false
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case _: OutAnnoAnnotation => false
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case _ => true
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})))
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outputFile.close()
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@@ -46,7 +46,7 @@ trait TapeoutCli {
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Seq(
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OutAnnoAnnotation,
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HarnessConfAnnotation,
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HarnessConfAnnotation
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).foreach(_.addOptions(parser))
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}
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@@ -66,4 +66,3 @@ class TapeoutStage(doHarness: Boolean) extends Stage {
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annotations
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}
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}
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