Merge pull request #648 from ucb-bar/sodor-integrate

Sodor Integration

.circleci/check-commit.sh

@@ -48,7 +48,7 @@ search () {
     done
 }
 
-submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip")
+submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor")
 dir="generators"
 if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ]
 then

.circleci/config.yml

@@ -241,6 +241,13 @@ jobs:
                 group-key: "group-cores"
                 project-key: "chipyard-ariane"
                 timeout: "30m"
+    chipyard-sodor-run-tests:
+        executor: main-env
+        steps:
+            - run-tests:
+                group-key: "group-cores"
+                project-key: "chipyard-sodor"
+                timeout: "30m"
     chipyard-dmirocket-run-tests:
         executor: main-env
         steps:
@@ -427,7 +434,9 @@ workflows:
             - chipyard-ariane-run-tests:
                 requires:
                     - prepare-chipyard-cores
-
+            - chipyard-sodor-run-tests:
+                requires:
+                    - prepare-chipyard-cores
             - chipyard-dmirocket-run-tests:
                 requires:
                     - prepare-chipyard-peripherals

.circleci/defaults.sh

@@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim
 
 # key value store to get the build groups
 declare -A grouping
-grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom"
+grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor"
 grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif"
 grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough"
 grouping["group-tracegen"]="tracegen tracegen-boom"
@@ -73,10 +73,10 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog"
 mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config"
 mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig"
 mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig"
+mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig"
 
 mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests"
 mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests"
 mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests"
 mapping["icenet"]="SUB_PROJECT=icenet"
 mapping["testchipip"]="SUB_PROJECT=testchipip"
-

.circleci/run-tests.sh

@@ -94,6 +94,9 @@ case $1 in
     chipyard-ariane)
         make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv
         ;;
+    chipyard-sodor)
+        run_asm ${mapping[$1]}
+        ;;
     chipyard-nvdla)
         make -C $LOCAL_CHIPYARD_DIR/tests
         make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary

.gitmodules

@@ -128,3 +128,6 @@
 [submodule "tools/dromajo/dromajo-src"]
 	path = tools/dromajo/dromajo-src
 	url = https://github.com/riscv-boom/dromajo.git
+[submodule "generators/riscv-sodor"]
+	path = generators/riscv-sodor
+	url = https://github.com/ucb-bar/riscv-sodor.git

build.sbt

@@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard"))
   .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell,
     sha3, // On separate line to allow for cleaner tutorial-setup patches
     dsptools, `rocket-dsptools`,
-    gemmini, icenet, tracegen, ariane, nvdla)
+    gemmini, icenet, tracegen, ariane, nvdla, sodor)
   .settings(commonSettings)
 
 lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen"))
@@ -158,6 +158,10 @@ lazy val ariane = (project in file("generators/ariane"))
   .dependsOn(rocketchip)
   .settings(commonSettings)
 
+lazy val sodor = (project in file("generators/riscv-sodor"))
+  .dependsOn(rocketchip)
+  .settings(commonSettings)
+
 lazy val sha3 = (project in file("generators/sha3"))
   .dependsOn(rocketchip, chisel_testers, midasTargetUtils)
   .settings(commonSettings)

docs/Generators/Sodor.rst

@@ -0,0 +1,17 @@
+Sodor Core
+====================================
+
+`Sodor <https://github.com/ucb-bar/riscv-sodor>`__ is a collection of 5 simple RV32MI cores designed for educational purpose.
+The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`.
+The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT**
+support external memory. 
+
+The five available cores and their corresponding generator configuration are:
+
+* 1-stage (essentially an ISA simulator) - ``Sodor1StageConfig``
+* 2-stage (demonstrates pipelining in Chisel) - ``Sodor2StageConfig``
+* 3-stage (uses sequential memory; supports both Harvard (``Sodor3StageConfig``) and Princeton (``Sodor3StageSinglePortConfig``) versions)
+* 5-stage (can toggle between fully bypassed or fully interlocked) - ``Sodor5StageConfig``
+* "bus"-based micro-coded implementation - ``SodorUCodeConfig``
+
+For more information, please refer to the `GitHub repository <https://github.com/ucb-bar/riscv-sodor>`__.

docs/Generators/index.rst

@@ -29,4 +29,5 @@ so changes to the generators themselves will automatically be used when building
    SHA3
    Ariane
    NVDLA
+   Sodor
 

generators/chipyard/src/main/scala/TestSuites.scala

@@ -92,8 +92,8 @@ class TestSuiteHelper
       }
       if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc))
       val (rvi, rvu) =
-        if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u)
+        if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui)))
-        else            ((if (vm) rv32i else rv32pi), rv32u)
+        else            ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui)))
 
       addSuites(rvi.map(_("p")))
       addSuites(rvu.map(_("p")))

generators/chipyard/src/main/scala/config/SodorConfigs.scala

@@ -0,0 +1,59 @@
+package chipyard
+
+import chisel3._
+
+import freechips.rocketchip.config.{Config}
+
+class Sodor1StageConfig extends Config(
+  // Create a Sodor 1-stage core
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)
+
+class Sodor2StageConfig extends Config(
+  // Create a Sodor 2-stage core
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)
+
+class Sodor3StageConfig extends Config(
+  // Create a Sodor 1-stage core with two ports
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)
+
+class Sodor3StageSinglePortConfig extends Config(
+  // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter)
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)
+
+class Sodor5StageConfig extends Config(
+  // Create a Sodor 5-stage core
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)
+
+class SodorUCodeConfig extends Config(
+  // Construct a Sodor microcode-based single-bus core
+  new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++
+  new testchipip.WithSerialPBusMem ++
+  new freechips.rocketchip.subsystem.WithScratchpadsOnly ++    // use sodor tile-internal scratchpad
+  new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory
+  new freechips.rocketchip.subsystem.WithNBanks(0) ++
+  new chipyard.config.AbstractConfig)

scripts/tutorial-patches/build.sbt.patch

@@ -9,7 +9,7 @@ index 5d642c1..56f6fda 100644
 -    sha3, // On separate line to allow for cleaner tutorial-setup patches
 +//    sha3, // On separate line to allow for cleaner tutorial-setup patches
      dsptools, `rocket-dsptools`,
-     gemmini, icenet, tracegen, ariane, nvdla)
+     gemmini, icenet, tracegen, ariane, nvdla, sodor)
    .settings(commonSettings)
 @@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane"))
    .dependsOn(rocketchip)