From 02a951703b0d6da5f5bff9118dc10ef49afa6cba Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 2 Jul 2020 00:52:51 -0700 Subject: [PATCH 01/32] Initialize riscv-sodor --- .gitmodules | 3 +++ generators/riscv-sodor | 1 + 2 files changed, 4 insertions(+) create mode 160000 generators/riscv-sodor diff --git a/.gitmodules b/.gitmodules index aab9a8f7..f374fa1f 100644 --- a/.gitmodules +++ b/.gitmodules @@ -128,3 +128,6 @@ [submodule "tools/dromajo/dromajo-src"] path = tools/dromajo/dromajo-src url = https://github.com/riscv-boom/dromajo.git +[submodule "generators/riscv-sodor"] + path = generators/riscv-sodor + url = https://github.com/ucb-bar/riscv-sodor.git diff --git a/generators/riscv-sodor b/generators/riscv-sodor new file mode 160000 index 00000000..73af1b70 --- /dev/null +++ b/generators/riscv-sodor @@ -0,0 +1 @@ +Subproject commit 73af1b7099764350c6dab6c5960334abcb7bdf07 From 85069387c9ccce5b12d86215b3fce10fe6679ea1 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 8 Jul 2020 14:45:12 -0700 Subject: [PATCH 02/32] Base Scratchpad --- build.sbt | 6 +++++- generators/riscv-sodor | 2 +- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/build.sbt b/build.sbt index 5d642c1d..750878ab 100644 --- a/build.sbt +++ b/build.sbt @@ -132,7 +132,7 @@ lazy val chipyard = conditionalDependsOn(project in file("generators/chipyard")) .dependsOn(boom, hwacha, sifive_blocks, sifive_cache, utilities, iocell, sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla) + gemmini, icenet, tracegen, ariane, nvdla, sodor) .settings(commonSettings) lazy val tracegen = conditionalDependsOn(project in file("generators/tracegen")) @@ -158,6 +158,10 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) .settings(commonSettings) +lazy val sodor = (project in file("generators/riscv-sodor")) + .dependsOn(rocketchip) + .settings(commonSettings) + lazy val sha3 = (project in file("generators/sha3")) .dependsOn(rocketchip, chisel_testers, midasTargetUtils) .settings(commonSettings) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 73af1b70..607f346f 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 73af1b7099764350c6dab6c5960334abcb7bdf07 +Subproject commit 607f346ff2e92977dcadda6cbd5b85589edcfbea From 1933fd8cbe21d697fafeebebabe50c775e65c55a Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 14 Jul 2020 12:10:12 -0700 Subject: [PATCH 03/32] Update sodor package structure --- .../src/main/scala/config/SodorConfigs.scala | 20 +++++++++++++++++++ generators/riscv-sodor | 2 +- 2 files changed, 21 insertions(+), 1 deletion(-) create mode 100644 generators/chipyard/src/main/scala/config/SodorConfigs.scala diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala new file mode 100644 index 00000000..dfcfebe7 --- /dev/null +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -0,0 +1,20 @@ +package chipyard + +import chisel3._ + +import freechips.rocketchip.config.{Config} + +class SodorConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter + new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts + new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) + new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing + new testchipip.WithTSI ++ // use testchipip serial offchip link + new chipyard.config.WithBootROM ++ // use default bootrom + new chipyard.config.WithUART ++ // add a UART + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts + new sodor.common.WithNSodorCores(1) ++ // single Ariane core + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 + new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 607f346f..5e6a775d 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 607f346ff2e92977dcadda6cbd5b85589edcfbea +Subproject commit 5e6a775ded0c19719f61acbae11874478bc9a8b5 From 7bb1a48b1a5eacfc942d6b3f461823ecb8fd17c8 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 16 Jul 2020 14:12:29 -0700 Subject: [PATCH 04/32] Connect TileLink nodes --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 5e6a775d..fbb9a9df 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 5e6a775ded0c19719f61acbae11874478bc9a8b5 +Subproject commit fbb9a9df0fb33f9228616902c1cf53083a73e6b6 From d56df6252c7d3f5ebe5eb630cf84e156b573d8b9 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 23 Jul 2020 19:24:44 -0700 Subject: [PATCH 05/32] Sync --- .../src/main/scala/config/SodorConfigs.scala | 30 +++++++++++-------- generators/riscv-sodor | 2 +- 2 files changed, 18 insertions(+), 14 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index dfcfebe7..1e1b7e51 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,16 +5,20 @@ import chisel3._ import freechips.rocketchip.config.{Config} class SodorConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ // display UART with a SimUARTAdapter - new chipyard.iobinders.WithTieOffInterrupts ++ // tie off top-level interrupts - new chipyard.iobinders.WithTiedOffDebug ++ // tie off debug (since we are using SimSerial for testing) - new chipyard.iobinders.WithSimSerial ++ // drive TSI with SimSerial for testing - new testchipip.WithTSI ++ // use testchipip serial offchip link - new chipyard.config.WithBootROM ++ // use default bootrom - new chipyard.config.WithUART ++ // add a UART - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ // no top-level MMIO master port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNoSlavePort ++ // no top-level MMIO slave port (overrides default set in rocketchip) - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ // no external interrupts - new sodor.common.WithNSodorCores(1) ++ // single Ariane core - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ // hierarchical buses including mbus+l2 - new freechips.rocketchip.system.BaseConfig) // "base" rocketchip system + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) \ No newline at end of file diff --git a/generators/riscv-sodor b/generators/riscv-sodor index fbb9a9df..f78d07e3 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit fbb9a9df0fb33f9228616902c1cf53083a73e6b6 +Subproject commit f78d07e387fcb90ae324bfdc5881b7f88e509248 From 14e2a9dbd1be267698f6eb0996a753de2e4f8921 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 24 Jul 2020 14:17:29 -0700 Subject: [PATCH 06/32] Fixed tile_master --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f78d07e3..c3423720 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f78d07e387fcb90ae324bfdc5881b7f88e509248 +Subproject commit c34237201ec83c24f33b4b5dbc02bd7f1368dfcd From 6131ab58e5b826598b4fb0b082e033c6235cacb8 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Tue, 28 Jul 2020 13:37:07 -0700 Subject: [PATCH 07/32] Connect cores --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index c3423720..e9b9aa4e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit c34237201ec83c24f33b4b5dbc02bd7f1368dfcd +Subproject commit e9b9aa4e0150aba1326644318243619c4899c9ae From 98ef89cbde8cd166fe39cfe96f55d45edd58006f Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 29 Jul 2020 15:02:33 -0700 Subject: [PATCH 08/32] Created Internal Tiles --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index e9b9aa4e..a4d5c5c0 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit e9b9aa4e0150aba1326644318243619c4899c9ae +Subproject commit a4d5c5c0e582146ec09d018af466fe5def979f3b From a2bd26b91cbef686d56460dab86861e7e32673c4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 31 Jul 2020 20:54:42 -0700 Subject: [PATCH 09/32] Finished Sodor Design --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index a4d5c5c0..eed11e8a 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit a4d5c5c0e582146ec09d018af466fe5def979f3b +Subproject commit eed11e8ab242d9144c3c6eb60e3fdd65218ade31 From 7f5b324d0639a058ee86d8066c2df0b9bd997f8e Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 5 Aug 2020 17:16:36 -0700 Subject: [PATCH 10/32] Added interrupt --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index eed11e8a..6c682077 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit eed11e8ab242d9144c3c6eb60e3fdd65218ade31 +Subproject commit 6c682077c1c541d0e66a05631483b76b6ac2d926 From 751215dec1cbfda4e879d77a8b7d5f1c8082fe1c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 12 Aug 2020 14:26:49 -0700 Subject: [PATCH 11/32] 5-stage core running --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 6c682077..7e7f2d4d 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 6c682077c1c541d0e66a05631483b76b6ac2d926 +Subproject commit 7e7f2d4df1b870b7a877648462b5aa6da0c7e207 From 03e50178f1f74e6f88225f3960749225f2ed0011 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 14 Aug 2020 16:00:38 -0700 Subject: [PATCH 12/32] Add misalignment detection & make M-extension test optional --- generators/chipyard/src/main/scala/TestSuites.scala | 4 ++-- generators/riscv-sodor | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/generators/chipyard/src/main/scala/TestSuites.scala b/generators/chipyard/src/main/scala/TestSuites.scala index 9ca2c08c..8cdfd3c9 100644 --- a/generators/chipyard/src/main/scala/TestSuites.scala +++ b/generators/chipyard/src/main/scala/TestSuites.scala @@ -92,8 +92,8 @@ class TestSuiteHelper } if (coreParams.useCompressed) addSuites(env.map(if (xlen == 64) rv64uc else rv32uc)) val (rvi, rvu) = - if (xlen == 64) ((if (vm) rv64i else rv64pi), rv64u) - else ((if (vm) rv32i else rv32pi), rv32u) + if (xlen == 64) ((if (vm) rv64i else rv64pi), (if (coreParams.mulDiv.isDefined) rv64u else List(rv64ui))) + else ((if (vm) rv32i else rv32pi), (if (coreParams.mulDiv.isDefined) rv32u else List(rv32ui))) addSuites(rvi.map(_("p"))) addSuites(rvu.map(_("p"))) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 7e7f2d4d..f6d5f45e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 7e7f2d4df1b870b7a877648462b5aa6da0c7e207 +Subproject commit f6d5f45e31cd2f8c4aad64662d7ec0d59545f344 From f6992c61c8bff041f78ca395f61de5048b80a15b Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 15 Aug 2020 00:20:47 -0700 Subject: [PATCH 13/32] 5-stage CPU passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f6d5f45e..cdc1dad8 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f6d5f45e31cd2f8c4aad64662d7ec0d59545f344 +Subproject commit cdc1dad8b0ef2b08ab595a198d1455cbd05a55d3 From 97f595f41582fcc961274cd2222d68fc4802b24d Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 16 Aug 2020 15:41:44 -0700 Subject: [PATCH 14/32] 1-stage passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index cdc1dad8..af19aa2f 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit cdc1dad8b0ef2b08ab595a198d1455cbd05a55d3 +Subproject commit af19aa2fc56a5a2e883b2880608f0e35a5498c49 From 84359abd19c034e42d395b5132a1dbe56ab132a2 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 16 Aug 2020 16:07:38 -0700 Subject: [PATCH 15/32] Isolated master adapter's TileLink valid signals from the core --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index af19aa2f..989c9831 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit af19aa2fc56a5a2e883b2880608f0e35a5498c49 +Subproject commit 989c98313c147b0c91614228dfc8b1dfb78c5200 From b0b09870ddf0ebc543383c1ee64495177d4d7c3c Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 17 Aug 2020 21:11:44 -0700 Subject: [PATCH 16/32] 2-stage core passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 989c9831..602ff66b 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 989c98313c147b0c91614228dfc8b1dfb78c5200 +Subproject commit 602ff66b0ef487df1d01c176eb3c62f8443b274e From 5c5af7bfaded370e08bede3514a557be5841f532 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 28 Aug 2020 18:37:47 -0700 Subject: [PATCH 17/32] Stage 3 passed all tests --- generators/riscv-sodor | 2 +- sims/verilator/Makefile | 5 ++--- 2 files changed, 3 insertions(+), 4 deletions(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 602ff66b..f2f87953 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 602ff66b0ef487df1d01c176eb3c62f8443b274e +Subproject commit f2f879533325964670c3086dfdfa1660e722551b diff --git a/sims/verilator/Makefile b/sims/verilator/Makefile index 3d676efd..531c2dd3 100644 --- a/sims/verilator/Makefile +++ b/sims/verilator/Makefile @@ -150,9 +150,8 @@ $(sim_debug): $(model_mk_debug) $(dramsim_lib) ######################################################################################### .PRECIOUS: $(output_dir)/%.vpd %.vcd $(output_dir)/%.vpd: $(output_dir)/% $(sim_debug) - rm -f $@.vcd && mkfifo $@.vcd - vcd2vpd $@.vcd $@ > /dev/null & - (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v$@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) + touch $@.vpd + (set -o pipefail && $(sim_debug) $(PERMISSIVE_ON) $(SIM_FLAGS) $(EXTRA_SIM_FLAGS) $(SEED_FLAG) $(VERBOSE_FLAGS) -v $@.vcd $(PERMISSIVE_OFF) $< >(spike-dasm > $<.out) | tee $<.log) ######################################################################################### # general cleanup rule From bb1d0a10ae12299de5872e93fbc0b76d0fd0f71b Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 31 Aug 2020 18:00:40 -0700 Subject: [PATCH 18/32] Stage 3 (single port) passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index f2f87953..477f9a4e 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit f2f879533325964670c3086dfdfa1660e722551b +Subproject commit 477f9a4eb9209cfc8eaae2f8e9f80f951c057342 From 0995f1b04b86d167578925d95da41f79f82fdd23 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 2 Sep 2020 21:25:36 -0700 Subject: [PATCH 19/32] UCode passed all tests --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 477f9a4e..4c3bab58 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 477f9a4eb9209cfc8eaae2f8e9f80f951c057342 +Subproject commit 4c3bab5885b7d9f3ce0d621c0c2918aa853e879c From 11dcd71a48161ea1e0fb78225c6fb778ad50936d Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sun, 6 Sep 2020 23:06:00 -0700 Subject: [PATCH 20/32] Clean up 5-stage instruction fetch --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 4c3bab58..e635b4ae 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 4c3bab5885b7d9f3ce0d621c0c2918aa853e879c +Subproject commit e635b4ae41d3d5ac570b8766877003e1c60f48ff From 15d53e2cda499f46c9f3ddc727ae35a95461ecce Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 9 Sep 2020 15:12:37 -0700 Subject: [PATCH 21/32] Bump to the latest Rocket --- .../src/main/scala/config/SodorConfigs.scala | 101 +++++++++++++++++- generators/riscv-sodor | 2 +- 2 files changed, 99 insertions(+), 4 deletions(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 1e1b7e51..335e7c4e 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -4,7 +4,7 @@ import chisel3._ import freechips.rocketchip.config.{Config} -class SodorConfig extends Config( +class Sodor1StageConfig extends Config( new chipyard.iobinders.WithUARTAdapter ++ new chipyard.iobinders.WithTieOffInterrupts ++ new chipyard.iobinders.WithTiedOffDebug ++ @@ -19,6 +19,101 @@ class SodorConfig extends Config( new freechips.rocketchip.subsystem.WithNoSlavePort ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ - new sodor.common.WithNSodorCores(1) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) \ No newline at end of file + new freechips.rocketchip.system.BaseConfig) + +class Sodor2StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor3StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor3StageSinglePortConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class Sodor5StageConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) + +class SodorUCodeConfig extends Config( + new chipyard.iobinders.WithUARTAdapter ++ + new chipyard.iobinders.WithTieOffInterrupts ++ + new chipyard.iobinders.WithTiedOffDebug ++ + new chipyard.iobinders.WithSimSerial ++ + new testchipip.WithTSI ++ + new chipyard.config.WithBootROM ++ + new chipyard.config.WithUART ++ + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new freechips.rocketchip.subsystem.WithNoMemPort ++ + new freechips.rocketchip.subsystem.WithNoMMIOPort ++ + new freechips.rocketchip.subsystem.WithNoSlavePort ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ + new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ + new freechips.rocketchip.system.BaseConfig) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index e635b4ae..70033f04 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit e635b4ae41d3d5ac570b8766877003e1c60f48ff +Subproject commit 70033f041a5e46fdc2c7c473fb8fa509bddc2e2d From 5506f776796dc54ca301c910dacfc3bbeb21adb4 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 14 Sep 2020 09:14:57 -0700 Subject: [PATCH 22/32] Add CircleCI check and update Sodor config --- .circleci/config.yml | 20 +++ .circleci/run-tests.sh | 3 + .../src/main/scala/config/SodorConfigs.scala | 120 ++++-------------- scripts/tutorial-patches/build.sbt.patch | 2 +- 4 files changed, 48 insertions(+), 97 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index eac8504a..7b09791c 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,6 +262,11 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" + prepare-chipyard-sodor: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor" prepare-icenet: executor: main-env steps: @@ -390,6 +395,12 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" + chipyard-sodor-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor" + timeout: "20m" chipyard-nvdla-run-tests: executor: main-env steps: @@ -511,6 +522,11 @@ workflows: - install-riscv-toolchain - install-verilator + - prepare-chipyard-sodor: + requires: + - install-riscv-toolchain + - install-verilator + - prepare-icenet: requires: - install-riscv-toolchain @@ -616,6 +632,10 @@ workflows: requires: - prepare-chipyard-ariane + - chipyard-sodor-run-tests: + requires: + - prepare-chipyard-sodor + - chipyard-nvdla-run-tests: requires: - prepare-chipyard-nvdla diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 3e7b0285..c0b932b6 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,6 +91,9 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; + chipyard-sodor) + run_asm ${mapping[$1]} + ;; chipyard-nvdla) make -C $LOCAL_CHIPYARD_DIR/tests make -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$LOCAL_CHIPYARD_DIR/tests/nvdla.riscv run-binary diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index 335e7c4e..df386dd9 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,115 +5,43 @@ import chisel3._ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor2StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor3StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor3StageSinglePortConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class Sodor5StageConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) class SodorUCodeConfig extends Config( - new chipyard.iobinders.WithUARTAdapter ++ - new chipyard.iobinders.WithTieOffInterrupts ++ - new chipyard.iobinders.WithTiedOffDebug ++ - new chipyard.iobinders.WithSimSerial ++ - new testchipip.WithTSI ++ - new chipyard.config.WithBootROM ++ - new chipyard.config.WithUART ++ - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // remove offchip mem port - new freechips.rocketchip.subsystem.WithNBanks(0) ++ - new freechips.rocketchip.subsystem.WithNoMemPort ++ - new freechips.rocketchip.subsystem.WithNoMMIOPort ++ - new freechips.rocketchip.subsystem.WithNoSlavePort ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNExtTopInterrupts(0) ++ new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ - new freechips.rocketchip.system.BaseConfig) + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithNBanks(0) ++ + new chipyard.config.AbstractConfig) diff --git a/scripts/tutorial-patches/build.sbt.patch b/scripts/tutorial-patches/build.sbt.patch index 6c1e3007..aa7f0bd4 100644 --- a/scripts/tutorial-patches/build.sbt.patch +++ b/scripts/tutorial-patches/build.sbt.patch @@ -9,7 +9,7 @@ index 5d642c1..56f6fda 100644 - sha3, // On separate line to allow for cleaner tutorial-setup patches +// sha3, // On separate line to allow for cleaner tutorial-setup patches dsptools, `rocket-dsptools`, - gemmini, icenet, tracegen, ariane, nvdla) + gemmini, icenet, tracegen, ariane, nvdla, sodor) .settings(commonSettings) @@ -158,9 +158,9 @@ lazy val ariane = (project in file("generators/ariane")) .dependsOn(rocketchip) From 642441e0a27171665ff3a2484b599d94e244f497 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Mon, 14 Sep 2020 23:54:52 -0700 Subject: [PATCH 23/32] Replaced memory and fixed 3-stage single port arbiter --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 70033f04..43985218 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 70033f041a5e46fdc2c7c473fb8fa509bddc2e2d +Subproject commit 43985218b8c91c9206018177d81e37e27267dbf6 From a43400acb9f0397c18c510d72827933fb1e65991 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 15:36:14 -0700 Subject: [PATCH 24/32] Update CI --- .circleci/config.yml | 94 +++++++++++++++++-- .circleci/defaults.sh | 6 +- .circleci/run-tests.sh | 14 ++- .../src/main/scala/config/SodorConfigs.scala | 30 +++--- generators/riscv-sodor | 2 +- 5 files changed, 124 insertions(+), 22 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7b09791c..a695cf28 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -262,11 +262,31 @@ jobs: steps: - prepare-rtl: project-key: "chipyard-ariane" - prepare-chipyard-sodor: + prepare-chipyard-sodor-stage1: executor: main-env steps: - prepare-rtl: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + prepare-chipyard-sodor-stage2: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage2" + prepare-chipyard-sodor-stage3: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage3" + prepare-chipyard-sodor-stage5: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-stage5" + prepare-chipyard-sodor-ucode: + executor: main-env + steps: + - prepare-rtl: + project-key: "chipyard-sodor-ucode" prepare-icenet: executor: main-env steps: @@ -395,11 +415,35 @@ jobs: - run-tests: project-key: "chipyard-ariane" timeout: "30m" - chipyard-sodor-run-tests: + chipyard-sodor-stage1-run-tests: executor: main-env steps: - run-tests: - project-key: "chipyard-sodor" + project-key: "chipyard-sodor-stage1" + timeout: "20m" + chipyard-sodor-stage2-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage2" + timeout: "20m" + chipyard-sodor-stage3-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage3" + timeout: "20m" + chipyard-sodor-stage5-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-stage5" + timeout: "20m" + chipyard-sodor-ucode-run-tests: + executor: main-env + steps: + - run-tests: + project-key: "chipyard-sodor-ucode" timeout: "20m" chipyard-nvdla-run-tests: executor: main-env @@ -522,7 +566,27 @@ workflows: - install-riscv-toolchain - install-verilator - - prepare-chipyard-sodor: + - prepare-chipyard-sodor-stage1: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage2: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage3: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-stage5: + requires: + - install-riscv-toolchain + - install-verilator + + - prepare-chipyard-sodor-ucode: requires: - install-riscv-toolchain - install-verilator @@ -632,9 +696,25 @@ workflows: requires: - prepare-chipyard-ariane - - chipyard-sodor-run-tests: + - chipyard-sodor-stage1-run-tests: requires: - - prepare-chipyard-sodor + - prepare-chipyard-sodor-stage1 + + - chipyard-sodor-stage2-run-tests: + requires: + - prepare-chipyard-sodor-stage2 + + - chipyard-sodor-stage3-run-tests: + requires: + - prepare-chipyard-sodor-stage3 + + - chipyard-sodor-stage5-run-tests: + requires: + - prepare-chipyard-sodor-stage5 + + - chipyard-sodor-ucode-run-tests: + requires: + - prepare-chipyard-sodor-ucode - chipyard-nvdla-run-tests: requires: diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 703737cd..62b9ceb4 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -69,4 +69,8 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" - +mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig" +mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig" +mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig" +mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig" +mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index c0b932b6..cd4afd23 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -91,7 +91,19 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/dhrystone.riscv ;; - chipyard-sodor) + chipyard-sodor-stage1) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage2) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage3) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-stage5) + run_asm ${mapping[$1]} + ;; + chipyard-sodor-ucode) run_asm ${mapping[$1]} ;; chipyard-nvdla) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index df386dd9..eb7b4086 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -5,43 +5,49 @@ import chisel3._ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( + // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor2StageConfig extends Config( + // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageConfig extends Config( + // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor3StageSinglePortConfig extends Config( + // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class Sodor5StageConfig extends Config( + // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) class SodorUCodeConfig extends Config( + // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ - new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use rocket l1 scratchpad - new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ + new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad + new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ new chipyard.config.AbstractConfig) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 43985218..69df2b01 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 43985218b8c91c9206018177d81e37e27267dbf6 +Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16 From 56d1d5b500178af08f7233cfdb463ce8fd0e0e08 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 22:42:19 -0700 Subject: [PATCH 25/32] Fix CI errors --- .circleci/config.yml | 14 +++++++++++++- 1 file changed, 13 insertions(+), 1 deletion(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index 7e8219a3..be39e21a 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -462,7 +462,19 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-run-tests: + - chipyard-sodor-stage1-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage2-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage3-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-stage5-run-tests: + requires: + - prepare-chipyard-cores + - chipyard-sodor-ucode-run-tests: requires: - prepare-chipyard-cores From a02700a1d4a39d433b2e3a2b0bdfad176d9375ed Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 18 Sep 2020 23:14:47 -0700 Subject: [PATCH 26/32] Add documentation for sodor --- docs/Generators/Sodor.rst | 17 +++++++++++++++++ docs/Generators/index.rst | 1 + generators/riscv-sodor | 2 +- 3 files changed, 19 insertions(+), 1 deletion(-) create mode 100644 docs/Generators/Sodor.rst diff --git a/docs/Generators/Sodor.rst b/docs/Generators/Sodor.rst new file mode 100644 index 00000000..7f4282eb --- /dev/null +++ b/docs/Generators/Sodor.rst @@ -0,0 +1,17 @@ +Sodor Core +==================================== + +`Sodor `__ is a collection of 5 simple RV32MI cores designed for educational purpose. +The `Sodor core` is wrapped in an tile during generation so it can be used as a component within the `Rocket Chip SoC generator`. +The cores contain a small scratchpad memory to which the program are loaded through a TileLink slave port, and the cores **DO NOT** +support external memory. + +The five available cores and their corresponding generator configuration are: + +* 1-stage (essentially an ISA simulator) - ``Sodor1StageConfig`` +* 2-stage (demonstrates pipelining in Chisel) - ``Sodor2StageConfig`` +* 3-stage (uses sequential memory; supports both Harvard (``Sodor3StageConfig``) and Princeton (``Sodor3StageSinglePortConfig``) versions) +* 5-stage (can toggle between fully bypassed or fully interlocked) - ``Sodor5StageConfig`` +* "bus"-based micro-coded implementation - ``SodorUCodeConfig`` + +For more information, please refer to the `GitHub repository `__. diff --git a/docs/Generators/index.rst b/docs/Generators/index.rst index be9c5e55..cebb17e5 100644 --- a/docs/Generators/index.rst +++ b/docs/Generators/index.rst @@ -29,4 +29,5 @@ so changes to the generators themselves will automatically be used when building SHA3 Ariane NVDLA + Sodor diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 69df2b01..12fa11e4 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 69df2b013f162cf4c450cdc3e7bbd6e7b9f2de16 +Subproject commit 12fa11e485c4854a48eec0561698dd0b32230243 From ae5fb8470bcfbd06772df0044a6a1a097648e749 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Sat, 19 Sep 2020 10:27:20 -0700 Subject: [PATCH 27/32] Remove unnecessary CI tests --- .circleci/config.yml | 47 +++--------------------------------------- .circleci/defaults.sh | 6 +----- .circleci/run-tests.sh | 14 +------------ 3 files changed, 5 insertions(+), 62 deletions(-) diff --git a/.circleci/config.yml b/.circleci/config.yml index be39e21a..4ee84ced 100644 --- a/.circleci/config.yml +++ b/.circleci/config.yml @@ -241,40 +241,12 @@ jobs: group-key: "group-cores" project-key: "chipyard-ariane" timeout: "30m" - chipyard-sodor-stage1-run-tests: + chipyard-sodor-run-tests: executor: main-env steps: - run-tests: group-key: "group-cores" - project-key: "chipyard-sodor-stage1" - timeout: "30m" - chipyard-sodor-stage2-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage2" - timeout: "30m" - chipyard-sodor-stage3-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage3" - timeout: "30m" - chipyard-sodor-stage5-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-stage5" - timeout: "30m" - chipyard-sodor-ucode-run-tests: - executor: main-env - steps: - - run-tests: - group-key: "group-cores" - project-key: "chipyard-sodor-ucode" + project-key: "chipyard-sodor" timeout: "30m" chipyard-dmirocket-run-tests: executor: main-env @@ -462,22 +434,9 @@ workflows: - chipyard-ariane-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-stage1-run-tests: + - chipyard-sodor-run-tests: requires: - prepare-chipyard-cores - - chipyard-sodor-stage2-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-stage3-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-stage5-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-sodor-ucode-run-tests: - requires: - - prepare-chipyard-cores - - chipyard-dmirocket-run-tests: requires: - prepare-chipyard-peripherals diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index 75101884..e3318d87 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -79,8 +79,4 @@ mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Test mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" -mapping["chipyard-sodor-stage1"]="SUB_PROJEET=Sodor1StageConfig" -mapping["chipyard-sodor-stage2"]="SUB_PROJEET=Sodor2StageConfig" -mapping["chipyard-sodor-stage3"]="SUB_PROJEET=Sodor3StageSinglePortConfig" -mapping["chipyard-sodor-stage5"]="SUB_PROJEET=Sodor5StageConfig" -mapping["chipyard-sodor-ucode"]="SUB_PROJEET=SodorUCodeConfig" +mapping["chipyard-sodor"]="CONFIG=Sodor5StageConfig" diff --git a/.circleci/run-tests.sh b/.circleci/run-tests.sh index 37b22b70..da5029b5 100755 --- a/.circleci/run-tests.sh +++ b/.circleci/run-tests.sh @@ -94,19 +94,7 @@ case $1 in chipyard-ariane) make run-binary-fast -C $LOCAL_SIM_DIR ${mapping[$1]} BINARY=$RISCV/riscv64-unknown-elf/share/riscv-tests/benchmarks/multiply.riscv ;; - chipyard-sodor-stage1) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage2) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage3) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-stage5) - run_asm ${mapping[$1]} - ;; - chipyard-sodor-ucode) + chipyard-sodor) run_asm ${mapping[$1]} ;; chipyard-nvdla) From 6641c1f983464b133114be6ead681f95559865c5 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 24 Sep 2020 22:42:49 -0700 Subject: [PATCH 28/32] Attempt to fix CI --- .circleci/check-commit.sh | 2 +- .circleci/defaults.sh | 4 ++-- generators/riscv-sodor | 2 +- 3 files changed, 4 insertions(+), 4 deletions(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 7824b943..2d393aae 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then diff --git a/.circleci/defaults.sh b/.circleci/defaults.sh index e3318d87..1b41e395 100755 --- a/.circleci/defaults.sh +++ b/.circleci/defaults.sh @@ -47,7 +47,7 @@ LOCAL_FIRESIM_DIR=$LOCAL_CHIPYARD_DIR/sims/firesim/sim # key value store to get the build groups declare -A grouping -grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom" +grouping["group-cores"]="chipyard-ariane chipyard-rocket chipyard-hetero chipyard-boom chipyard-sodor" grouping["group-peripherals"]="chipyard-dmirocket chipyard-blkdev chipyard-spiflashread chipyard-spiflashwrite chipyard-mmios chipyard-lbwif" grouping["group-accels"]="chipyard-nvdla chipyard-sha3 chipyard-hwacha chipyard-gemmini chipyard-streaming-fir chipyard-streaming-passthrough" grouping["group-tracegen"]="tracegen tracegen-boom" @@ -73,10 +73,10 @@ mapping["chipyard-mmios"]=" CONFIG=MMIORocketConfig verilog" mapping["tracegen"]=" CONFIG=NonBlockingTraceGenL2Config" mapping["tracegen-boom"]=" CONFIG=BoomTraceGenConfig" mapping["chipyard-nvdla"]=" CONFIG=SmallNVDLARocketConfig" +mapping["chipyard-sodor"]=" CONFIG=Sodor5StageConfig" mapping["firesim"]="SCALA_TEST=firesim.firesim.RocketNICF1Tests" mapping["firesim-multiclock"]="SCALA_TEST=firesim.firesim.RocketMulticlockF1Tests" mapping["fireboom"]="SCALA_TEST=firesim.firesim.BoomF1Tests" mapping["icenet"]="SUB_PROJECT=icenet" mapping["testchipip"]="SUB_PROJECT=testchipip" -mapping["chipyard-sodor"]="CONFIG=Sodor5StageConfig" diff --git a/generators/riscv-sodor b/generators/riscv-sodor index 12fa11e4..b36ce1a7 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit 12fa11e485c4854a48eec0561698dd0b32230243 +Subproject commit b36ce1a7958a748c90508be6822a05c8208cd184 From f7407709d2a51c5946e1b84e6420651de5cc5802 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Fri, 25 Sep 2020 21:31:12 -0700 Subject: [PATCH 29/32] Attempt to fix CI (2) --- .../chipyard/src/main/scala/config/SodorConfigs.scala | 6 ++++++ generators/testchipip | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/generators/chipyard/src/main/scala/config/SodorConfigs.scala b/generators/chipyard/src/main/scala/config/SodorConfigs.scala index eb7b4086..ea245fbc 100644 --- a/generators/chipyard/src/main/scala/config/SodorConfigs.scala +++ b/generators/chipyard/src/main/scala/config/SodorConfigs.scala @@ -7,6 +7,7 @@ import freechips.rocketchip.config.{Config} class Sodor1StageConfig extends Config( // Create a Sodor 1-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage1Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -15,6 +16,7 @@ class Sodor1StageConfig extends Config( class Sodor2StageConfig extends Config( // Create a Sodor 2-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage2Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -23,6 +25,7 @@ class Sodor2StageConfig extends Config( class Sodor3StageConfig extends Config( // Create a Sodor 1-stage core with two ports new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 2)) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -31,6 +34,7 @@ class Sodor3StageConfig extends Config( class Sodor3StageSinglePortConfig extends Config( // Create a Sodor 3-stage core with one ports (instruction and data memory access controlled by arbiter) new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage3Factory(ports = 1)) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -39,6 +43,7 @@ class Sodor3StageSinglePortConfig extends Config( class Sodor5StageConfig extends Config( // Create a Sodor 5-stage core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.Stage5Factory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ @@ -47,6 +52,7 @@ class Sodor5StageConfig extends Config( class SodorUCodeConfig extends Config( // Construct a Sodor microcode-based single-bus core new sodor.common.WithNSodorCores(1, internalTile = sodor.common.UCodeFactory) ++ + new testchipip.WithSerialPBusMem ++ new freechips.rocketchip.subsystem.WithScratchpadsOnly ++ // use sodor tile-internal scratchpad new freechips.rocketchip.subsystem.WithNMemoryChannels(0) ++ // use no external memory new freechips.rocketchip.subsystem.WithNBanks(0) ++ diff --git a/generators/testchipip b/generators/testchipip index bdca33ec..bd0ff2d0 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bdca33ec1684e6e00df2f5c9aebc0b41fb593585 +Subproject commit bd0ff2d0c61023549304709ce0d377a837564295 From ef03a5efe0a652ff7fd19ff8b18e9661a12b8fcc Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Wed, 30 Sep 2020 14:36:45 -0700 Subject: [PATCH 30/32] Bump testchipip --- generators/testchipip | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/testchipip b/generators/testchipip index bd0ff2d0..10351d36 160000 --- a/generators/testchipip +++ b/generators/testchipip @@ -1 +1 @@ -Subproject commit bd0ff2d0c61023549304709ce0d377a837564295 +Subproject commit 10351d36a961d89e6f5ac1177dff0e9f3efb8c0f From 6c33672c664b7990cd443f27d93c977c55817c01 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 1 Oct 2020 10:08:39 -0700 Subject: [PATCH 31/32] Bump Sodor submodule after merge --- generators/riscv-sodor | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/generators/riscv-sodor b/generators/riscv-sodor index b36ce1a7..d92a8476 160000 --- a/generators/riscv-sodor +++ b/generators/riscv-sodor @@ -1 +1 @@ -Subproject commit b36ce1a7958a748c90508be6822a05c8208cd184 +Subproject commit d92a8476e4afbae189381d708136aef7d3970952 From 93a06cc5e7ceeb888cb32f6e3efd0418083f6d38 Mon Sep 17 00:00:00 2001 From: Zitao Fang Date: Thu, 1 Oct 2020 10:11:04 -0700 Subject: [PATCH 32/32] Fix CI master check --- .circleci/check-commit.sh | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.circleci/check-commit.sh b/.circleci/check-commit.sh index 2d393aae..68cc975c 100755 --- a/.circleci/check-commit.sh +++ b/.circleci/check-commit.sh @@ -48,7 +48,7 @@ search () { done } -submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "sodor") +submodules=("ariane" "boom" "gemmini" "hwacha" "icenet" "nvdla" "rocket-chip" "sha3" "sifive-blocks" "sifive-cache" "testchipip" "riscv-sodor") dir="generators" if [ "$CIRCLE_BRANCH" == "master" ] || [ "$CIRCLE_BRANCH" == "dev" ] then