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More fixes for RC bump

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This commit is contained in:
Jerry Zhao
2020-06-19 14:44:07 -07:00
parent f87522bf0e
commit 2bfc4f6dd4
3 changed files with 7 additions and 7 deletions
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2
generators/boom

Submodule generators/boom updated: 0b60c27879...96ac46f602

10
generators/chipyard/src/main/scala/config/TracegenConfigs.scala
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@@ -9,7 +9,7 @@ class TraceGenConfig extends Config(
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 0, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenConfig extends Config( class NonBlockingTraceGenConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
@@ -17,7 +17,7 @@ class NonBlockingTraceGenConfig extends Config(
new chipyard.config.WithTracegenSystem ++ new chipyard.config.WithTracegenSystem ++
new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++ new tracegen.WithTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 2, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class BoomTraceGenConfig extends Config( class BoomTraceGenConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
@@ -26,7 +26,7 @@ class BoomTraceGenConfig extends Config(
new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++ new tracegen.WithBoomTraceGen()(List.fill(2) { DCacheParams(nMSHRs = 8, nSets = 16, nWays = 2) }) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenL2Config extends Config( class NonBlockingTraceGenL2Config extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
@@ -35,7 +35,7 @@ class NonBlockingTraceGenL2Config extends Config(
new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++ new tracegen.WithL2TraceGen()(List.fill(2)(DCacheParams(nMSHRs = 2, nSets = 16, nWays = 4))) ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)
class NonBlockingTraceGenL2RingConfig extends Config( class NonBlockingTraceGenL2RingConfig extends Config(
new chipyard.iobinders.WithBlackBoxSimMem ++ new chipyard.iobinders.WithBlackBoxSimMem ++
@@ -45,4 +45,4 @@ class NonBlockingTraceGenL2RingConfig extends Config(
new testchipip.WithRingSystemBus ++ new testchipip.WithRingSystemBus ++
new freechips.rocketchip.subsystem.WithInclusiveCache ++ new freechips.rocketchip.subsystem.WithInclusiveCache ++
new freechips.rocketchip.subsystem.WithCoherentBusTopology ++ new freechips.rocketchip.subsystem.WithCoherentBusTopology ++
new freechips.rocketchip.system.BaseConfig) new freechips.rocketchip.groundtest.GroundTestBaseConfig)

2
generators/testchipip

Submodule generators/testchipip updated: 26891fac1d...29eb87c938